MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 605

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

24.11.4.2 Operational Model For Setup Transfers
As discussed in
treatment by the DCD. A setup transfer does not use a dTD but instead stores the incoming data from a
setup packet in an 8-byte buffer within the dQH.
Upon receiving notification of the setup packet, the DCD should handle the setup transfer as demonstrated
here:
24.11.5 Managing Transfers with Transfer Descriptors
24.11.5.1 Software Link Pointers
It is necessary for the DCD software to maintain head and tail pointers to the for the linked list of dTDs
for each respective queue head. This is necessary because the dQH only maintains pointers to the current
working dTD and the next dTD to be executed. The operations described in next section for managing dTD
will assume the DCD can use reference the head and tail of the dTD linked list.
Freescale Semiconductor
1. Copy setup buffer contents from dQH—RX to the software buffer.
2. Acknowledge setup backup by writing a 1 to the corresponding bit in ENDPTSETUPSTAT.
3. Check for pending data or status dTD's from previous control transfers and flush if any exist as
4. Decode setup packet and prepare data phase [optional] and status phase transfer as required by the
discussed in
USB Chapter 9 or application specific protocol.
The acknowledge must occur before continuing to process the setup packet.
After the acknowledge has occurred, the DCD must not attempt to access
the setup buffer in the dQH—RX. Only the local software copy should be
examined.
It is possible for the device controller to receive setup packets before
previous control transfers complete. Existing control packets in progress
must be flushed and the new control packet completed.
To conserve memory, the reserved fields at the end of the dQH can be used
to store the Head and Tail pointers but it still remains the responsibility of
the DCD to maintain the pointers.
Section 24.11.3.5, “Control Endpoint Operation Model,”
Section 24.11.5.5, “Flushing/De-Priming an
MCF5253 Reference Manual, Rev. 1
NOTE
NOTE
NOTE
NOTE
Endpoint.”
setup transfer requires special
Universal Serial Bus Interface
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