MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 402

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Background Debug Mode (BDM) Interface
20.5.3
The PC breakpoint registers (PBR and PBMR) define a region in the code address space of the processor
that can be used as part of the trigger. The PBR value is masked by the PBMR value, allowing only those
bits in PBR that have a corresponding zero in PBMR to be compared with the processor’s program counter
register, as defined in the TDR. The PBR is accessible in supervisor mode as debug control register $8
using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG
20-32
Field
6–5
4–3
2–0
TM
SZ
TT
Program Counter Breakpoint Register (PBR, PBMR)
The Size field is compared to the size signals of the processor’s local bus. These signals indicate the data
size for the bus transfer.
00 Longword
01 Byte
10 Word
11 Reserved
The transfer type field is compared with the transfer type signals of the processor’s local bus. These signals
indicate the transfer type for the bus transfer. These signals are always encoded as if the ColdFire is in the
ColdFire IACK mode.
00 Normal Processor Access
01 Reserved
10 Emulator Mode Access
11 Acknowledge/CPU Space Access
These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding
generates an alternate master access (for backward compatibility).
The transfer modifier field is compared with the transfer modifier signals of the processor’s local bus. The
signals provide supplemental information for each transfer type.
The encoding for normal processor transfers (TT = 0) is:
000 Explicit Cache Line Push
001 User Data Access
010 User Code Access
011 Reserved
100 Reserved
101 Supervisor Data Access
110 Supervisor Code Access
111 Reserved
The encoding for emulator mode transfers (TT = 10) is:
0xx Reserved
100 Reserved
101 Emulator Mode Data Access
110 Emulator Mode Code Access
111 Reserved
The encoding for acknowledge/CPU space transfers (TT = 11) is:
000 CPU Space Access
001 Interrupt Acknowledge Level 1
010 Interrupt Acknowledge Level 2
011 Interrupt Acknowledge Level 3
100 Interrupt Acknowledge Level 4
101 Interrupt Acknowledge Level 5
110 Interrupt Acknowledge Level 6
111 Interrupt Acknowledge Level 7
These bits also define the TM encoding for BDM memory commands (For backward compatibility).
Table 20-19. Address Attribute Trigger Register Field Descriptions
MCF5253 Reference Manual, Rev. 1
Description
Freescale Semiconductor