MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 319

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MCF5253VM140J

Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr

Specifications of MCF5253VM140J

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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Part Number:
MCF5253VM140J
Manufacturer:
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Quantity:
10 000
The CD subcode stream embedded into the IEC958 User channel consists of a sequence of packets. Every
packet contains 98 symbols. The first two symbols of every packet are sync symbols and the other 96
symbols are data symbols.
Any sequence found in the IEC958 U-channel stream starting with a leading one, followed by 7
information bits, is recognized as a data symbol. Subsequent data symbols are separated by pauses. During
the pause, zero bits are seen on the IEC958 U-channel.
Data symbols come in MSB first. The MSB is the leading one and is always received as bit 7.
When a long pause is seen between 2 subsequent data symbols, the IEC958 receiver assumes the reception
of one or more sync symbols.
The recognition of the number of sync symbols derives from the fact that the U-channel transmitter in the
CD channel decoder will transmit one symbol on average every 12 IEC958 channel bits. On this average
rate, there is a tolerance of 5% maximum.
The IEC958 receiver is tolerant on symbol error. Due to the physical nature of the transmission of the data
over the CD disc, not more than one out of any 5 consecutive user channel symbols may be in error. The
error may cause a change in data value, which is not treated by this interface, or it may cause a data symbol
to be seen as a sync symbol, or a sync symbol to be seen as a data symbol. However, not more than one
out of any 5 consecutive user channel symbols can be affected in this way.
The IEC958 User channel circuitry will recognize the 98-symbol packet structure. The 96 symbol payload
is transferred using 2 registers as follows:
Freescale Semiconductor
The UChannelRcv register—In this register, data is presented 4 symbols at a time. Every time 4
new valid symbols, received on the IEC958 U-Channel, are present, the UChannelRcvFull
interrupt is asserted. For one 98-symbol packet, 96 symbols are carried across UChannelRcv. To
transfer all this data, 24 UChannelRcvFull interrupts are generated.
The QChannelRcv register—In this register, only the Q bit of the packet is accumulated. Operation
is similar to UChannelRcv. Because only Q-bit is transferred, only 96 Q-bits are transferred for any
98-symbol packet. To transfer this data, 3 QChannelRcvFull interrupts are generated. When
QChannelRcvFull occurs, it is coincident with UChannelRcvFull. There is only one
QChannelRcvFull for every 8 UChannelRcvFull. The convention is that the most significant data
is transmitted first, and is left-aligned in the registers.
No of U Channel Zero Bits
Table 17-10. Correlation Between Zero Bits and Sync Symbols
11–22
23–34
35–45
2–10
> 45
0–1
Table 17-10
MCF5253 Reference Manual, Rev. 1
shows this functionality.
Corresponding Number of Sync Symbols
Unpredictable, not allowed
Unpredictable, not allowed
0
1
2
3
Audio Interface Module (AIM)
17-21

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