MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 261

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
RxRTS
RxIRQ
Field
ERR
4–3
PM
Address MBAR + $1C0 (UMR10)
7
6
5
Reset
W
R
Receiver Request-to-Send Control
1 On receipt of a valid start bit, RTS is negated if the UART FIFO is full. RTS is reasserted when the FIFO has an
0 The receiver has no effect on RTS. The RTS is asserted by writing a one to the Output Port Bit Set Register
This feature can be used for flow control to prevent overrun in the receiver by using the RTS output to control the
CTS input of the transmitting device. If both the receiver and transmitter are programmed for RTS control, RTS
control is disabled for both because such a configuration is incorrect.
Note: Not available on UART2.
RxIRQ—Receiver Interrupt Select
1 FFULL is the source that generates IRQ
0 RxRDY is the source that generates IRQ
The Error Mode bit controls the meaning of the three FIFO status bits (RB, FE, and PE) in the USR.
1 Block mode—The values in the channel USR are the accumulation (i.e., the logical OR) of the status for all
0 Character mode—The values in the channel USR reflect the status of the character at the top of the FIFO.
ERR = 0 must be used to obtain the correct A/D flag information when in multidrop mode.
The Parity Mode bits encode the type of parity used for the channel (see
transmitted character and the receiver performs a parity check on incoming data. These bits can alternatively select
multidrop mode for the channel.
MBAR + $200 (UMR11)
MBAR2 + $C00 (UMR12)
empty position available.
(UOP1)
characters coming to the top of the FIFO since the last reset error status command for the channel was issued.
Refer to
RXRTS
0
7
Section 15.4.17.1, “UART Module Initialization,”
Table 15-2. Mode Register 1 (UMR1n) Field Descriptions
RXIRQ
0
6
Figure 15-9. Mode Register 1 (UMR1n)
MCF5253 Reference Manual, Rev. 1
ERR
0
5
PM1
0
4
Description
for more information on UART module commands.
PM0
0
3
Table
Access: Supervisor or User read/write
PT
0
2
15-3). The parity bit is added to the
B/C1
0
1
UART Modules
B/C0
0
0
15-15