MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 52

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Signal Description
Bits 23 down to 1 and 24 of the address are available. A24 is intended to be used with 256 Mbit DRAM’s.
Signals are named:
2.3.2
This signal indicates during any bus cycle whether a read or write is in progress. A low is write cycle and
a high is a read cycle.
2.3.3
The OE signal is intended to be connected to the output enable of asynchronous memories connected to
chip selects. During bus read cycles, the ColdFire processor will drive OE low.
2.3.4
The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the MCF5253 on the
rising clock edge. The data bus uses a default configuration if none of the chip-selects or DRAM bank
match the address decode. All 16 bits of the data bus are driven during writes, regardless of port width or
operand size.
2.3.5
The TA/GPIO12 pin is the transfer acknowledge signal.
2.4
The following SDRAM signals provide a glueless interface to external SDRAM. An SDRAM width of 16
bits is supported and can access as much as 32MBs of memory. ADRAMs are not supported.
2-6
Synchronous DRAM row address strobe The SDRAS/GPIO59 active low pin provides a seamless interface to the RAS input
•
•
Synchronous DRAM chip enable
Synchronous DRAM UDQM and
Synchronous DRAM write
A[23:1]
A20/24
column address strobe
Synchronous DRAM
SDRAM Controller Signals
SDRAM Signal
LQDM signals
Read-Write Control
Output Enable
Data Bus
Transfer Acknowledge
Table 2-2. SDRAM Controller Signals
on synchronous DRAM
The SDCAS/GPIO39 active low pin provides a seamless interface to CAS input on
synchronous DRAM.
The SDWE/GPIO38 active-low pin is asserted to signify that a SDRAM write cycle is
underway. This pin outputs logic ‘1’ during read bus cycles.
The SD_CS0/GPIO60 active-low output signal is used during synchronous mode to
route directly to the chip select of a SDRAM device.
The DRAM byte enables UDMQ and LDQM are driven by the SDUDQM/GPO53 and
SDLDQM/GPO52 byte enable outputs.
MCF5253 Reference Manual, Rev. 1
Description
Freescale Semiconductor