MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 541

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
The iTD and siTD data structures each describe 8 micro-frames worth of transactions. The host controller
is allowed to cache one (or more) of these data structures in order to reduce memory traffic. There are three
basic caching models that account for the fact the isochronous data structures span 8 micro-frames. The
three caching models are: no caching, micro-frame caching and frame caching.
When the software is adding new isochronous transactions to the schedule, it always performs a read of
the FRINDEX register to determine the current frame and micro-frame the host controller is currently
executing. Of course, there is no information about where in the micro-frame the host controller is, so a
constant uncertainty factor of one micro-frame has to be assumed. Combining the knowledge of where the
host controller is executing with the knowledge of the caching model allows the definition of simple
algorithms for how closely the software can reliably work to the executing host controller.
No caching is indicated with a value of zero in the Isochronous Scheduling Threshold field. The host
controller may pre-fetch data structures during a periodic schedule traversal (per micro-frame) but will
always dump any accumulated schedule state at the end of the micro-frame. At the appropriate time
relative to the beginning of every micro-frame, the host controller always begins schedule traversal from
the frame list. The software can use the value of the FRINDEX register (plus the constant 1
uncertainty-factor) to determine the approximate position of the executing host controller. When no
caching is selected, the software can add an isochronous transaction as near as 2 micro-frames in front of
the current executing position of the host controller.
Frame caching is indicated with a non-zero value in bit [7] of the Isochronous Scheduling Threshold field.
In the frame-caching model, the system software assumes that the host controller caches one (or more)
isochronous data structures for an entire frame (8 micro-frames). The software uses the value of the
FRINDEX register (plus the constant 1 uncertainty) to determine the current micro-frame/frame (assume
modulo 8 arithmetic in adding the constant 1 to the micro-frame number). For any current frame N, if the
current micro-frame is 0 to 6, then the software can safely add isochronous transactions to Frame N + 1.
If the current micro-frame is 7, then software can add isochronous transactions to Frame N + 2.
Micro-frame caching is indicated with a non-zero value in the least-significant 3 bits of the Isochronous
Scheduling Threshold field. The system software assumes the host controller caches one or more periodic
data structures for the number of micro-frames indicated in the Isochronous Scheduling Threshold field.
For example, if the count value were 2, then the host controller keeps a window of 2 micro-frames worth
of state (current micro-frame, plus the next) on-chip. On each micro-frame boundary, the host controller
releases the current micro-frame state and begins accumulating the next micro-frame state.
24.9.9
Asynchronous Schedule
The Asynchronous schedule traversal is enabled or disabled via the Asynchronous Schedule Enable bit in
the USBCMD register. If the Asynchronous Schedule Enable bit is cleared, then the host controller simply
does not try to access the asynchronous schedule via the ASYNCLISTADDR register. Likewise, if the
Asynchronous Schedule Enable bit is set, the host controller does use the ASYNCLISTADDR register to
traverse the asynchronous schedule. Modifications to the Asynchronous Schedule Enable bit are not
necessarily immediate. Rather the new value of the bit will only be taken into consideration the next time
the host controller needs to use the value of the ASYNCLISTADDR register to get the next queue head.
The Asynchronous Schedule Status bit in the USBSTS register indicates status of the asynchronous
schedule. The system software enables (or disables) the asynchronous schedule by writing a one (or zero)
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
24-79