MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 139

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Figure 8-8
control register (CSCRs) to give the peripheral or memory more time to return read data. This figure
follows the same execution as a zero-wait state read burst with the exception of an added wait state.
Freescale Semiconductor
shows a line access read with one wait state. Wait states can be programmed in the chip select
The bus cycle begins similar to a basic read bus cycle with the first data
transfer being sampled on the rising edge of S4. However, also notice that
the next pipelined burst data is sampled one cycle later on the rising edge of
S6. Each subsequent pipelined data burst will be single cycle until the last
cycle which can be held for a maximum of 2 BCLK past the TA assertion.
CS and OE remain asserted throughout the burst transfer.
Figure 8-9. Line Read Burst (no wait cycles) Line Write Bus Cycles
Figure 8-8. Line Read Burst (one wait cycle)
MCF5253 Reference Manual, Rev. 1
NOTE
Bus Operation
8-11