MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 256

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

UART Modules
In either mode, reading the USR does not affect the FIFO. The FIFO is popped only when the receive
buffer is read. The USR should be read prior to reading the receive buffer. If all three of the FIFO receiver
holding registers are full when a new character is received, the new character is held in the receiver shift
register until a FIFO position is available. If an additional character is received during this state, the
contents of the FIFO are not affected. However, the previous character in the receiver shift register is lost
and the OE bit in the USR is set when the receiver detects the start bit of the new overrunning character.
To support flow control capability, the receiver can be programmed to automatically negate and assert
1
RTS
. When in this mode, the receiver automatically negates RTS when a valid start bit is detected and the
FIFO is full. When a FIFO position becomes available, the receiver asserts RTS. Using this mode of
operation prevents overrun errors by connecting the RTS to the CTS input of the transmitting device.
To use the RTS signals on UART1, the Pin Configuration Register in the SIM must be set up to enable the
corresponding I/O pins for these functions. If the FIFO contains characters and the receiver is disabled, the
CPU can still read the characters in the FIFO. If the receiver is reset, the FIFO and all receiver status bits,
corresponding output ports, and interrupt request are reset. No additional characters are received until the
receiver is re-enabled.
15.3.3
Looping Modes
The UART can be configured to operate in various looping modes as shown in
Figure
15-7. These modes
are useful for local and remote system diagnostic functions. The modes are described in the following
paragraphs with additional information available in
Section 15.4, “UART Memory Map and Register
Definitions.”
Switching between modes should only be done while the transmitter and receiver are disabled because the
selected mode is activated immediately on mode selection, even if this occurs in the middle of character
transmission or reception. In addition, if a mode is deselected, the device switches out of the mode
immediately, except for automatic echo and remote echo loopback modes. In these modes, the deselection
occurs just after the receiver has sampled the stop bit (this is also the one-half point). For automatic echo
mode, the transmitter stays in this mode until the entire stop bit has been retransmitted.
15.3.3.1
Automatic Echo Mode
In this mode, the UART automatically retransmits the received data on a bit-by-bit basis. The local
CPU-to-receiver communication continues normally but the CPU-to-transmitter link is disabled. While in
this mode, received data is clocked on the receiver clock and retransmitted on TxD. The receiver must be
enabled but not the transmitter. Instead, the transmitter is clocked by the receiver clock.
Because the transmitter is not active, the TxEMP and TxRDY bits in USR are inactive and data is
transmitted as it is received. Received parity is checked but not recalculated for transmission. Character
framing is also checked but stop bits are transmitted as received. A received break is echoed as received
until the next valid start bit is detected.
1. CTS and RTS are not available on UART2.
MCF5253 Reference Manual, Rev. 1
15-10
Freescale Semiconductor