MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 147

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

9.3
This section provides the Module Base Address, DeviceID, and Interrupt Controller registers and their
descriptions.
9.3.1
The base address of all internal peripherals is determined by the MBAR and MBAR2 registers.
The MBAR and MBAR2 are 32-bit write-only supervisor control registers that physically reside in the
SIM. They are accessed in the CPU address spaces $C0F and $C0E using the MOVEC instruction. Refer
to the ColdFire Family Programmer’s Reference Manual for use of MOVEC instruction. The MBAR and
MBAR2 can be read when in debug mode using background debug commands.
At system reset, the MBAR valid bits (MBAR[0], MBAR2[0]) are cleared to prevent incorrect reference
to resources before the MBAR or MBAR2 are written. The remainder of the MBAR and MBAR2 bits are
Freescale Semiconductor
MBAR2 + $0BC
MBAR2 + $00C
MBAR2 + $0B0
MBAR2 + $0B4
MBAR2 + $0B8
MBAR2 + $14C
MBAR2 + $15C
MBAR2 + $000
MBAR2 + $004
MBAR2 + $008
MBAR2 + $140
MBAR2 + $144
MBAR2 + $148
MBAR2 + $150
MBAR2 + $154
MBAR2 + $158
MBAR2 + $164
MBAR2 + $168
MBAR2 + $198
MBAR + $0AC
MBAR + $054
Address
SIM Module Programming Registers
Module Base Address Registers
Primary Interrupt Control Reg
GPIO 0
GPIO 0
GPIO 0
GPIO 0
DeviceID Reg
GPIO 32
GPIO 32
GPIO 32
GPIO 32
Secondary interrupts 0
Secondary interrupts 8
Secondary interrupts 16
Secondary interrupts 24
Secondary interrupts 32
Secondary interrupts 40
Secondary interrupts 48
Secondary interrupts 56
Spurious secondary interrupt vector
Secondary interrupt base vector register
Software interrupts and interrupt monitor
–
–
–
–
–
–
–
–
31 input reg
31 output reg
31 output enable reg
31 function select
63 input reg
63 output reg
63 output enable reg
63 function select
Table 9-2. SIM Memory Map (continued)
Description
MCF5253 Reference Manual, Rev. 1
–
–
–
–
–
–
–
–
7 priority
15 priority
23 priority
31 priority
39 priority
47 priority
55 priority
63 priority
ICR8
GPIO-READ (READ ONLY)
GPIO-OUT
GPIO-ENABLE
GPIO-FUNCTION
GPIO1-READ (READ ONLY)
GPIO1-OUT
GPIO1-ENABLE
GPIO1-FUNCTION
INTPRI1
INTPRI2
INTPRI3
INTPRI4
INTPRI5
INTPRI6
INTPRI7
INTPRI8
SPURVEC
INTBASE
EXTRAINT
0
ICR9
1
System Integration Module (SIM)
–
ICR10
2
ICR11
3
9-3