MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 28

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Chapter 9, “System Integration Module
Chapter 10, “Chip Select
Chapter 11, “General Purpose Timer
Chapter 12, “Analog to Digital Converter
Chapter 13, “IDE and Flash Media
Chapter 14, “DMA
Chapter 15, “UART
Chapter 16, “Queued Serial Peripheral Interface (QSPI)
Chapter 17, “Audio Interface Module
Chapter 18, “I2C
Chapter 19, “Boot
Chapter 20, “Background Debug Mode (BDM)
xxviii
Modules”:
ROM”:
Controller”:
Modules”:
bus master. This chapter includes descriptions of the error conditions, bus
arbitration, and the reset operation.
register definitions of the System Integration Module (SIM) registers, including
the interrupt controller and system-protection functions for the MCF5253. The
SIM provides overall control of the internal and external buses and serves as the
interface between the ColdFire® core and the internal peripherals or external
devices. The SIM also configures the general purpose input/output and enables the
CPU HALT instruction.
three chip select outputs, two buffer enable outputs and one output-enable signal.
This chapter describes the operation, memory map, and register definitions of the
chip-select registers, including the chip select address, mask, and control registers.
the two general purpose timer modules (Timer0 and Timer1). Also provided are
the memory map and register definitions as well as example initialization code.
map, register definitions, and setup recommendations of external components.
IDE and Flash Media, the interface setup, timing and operation are provided as
well as commonly used commands.
register definitions, as well as discussing transfer generation, transfer modes, and
the transfer function.
register definitions, and initialization sequence of the three UART modules.
the Queued Serial Peripheral interface module and provides its memory map and
register definitions. The QSPI module provides a serial peripheral interface with
queued transfer capability. It allows users to queue up to 16 transfers at once,
eliminating CPU intervention between transfers.
memory map, and register definitions, as well as transmit and receive interfaces.
The audio interface module provides the necessary input and output features to
receive and transmit digital audio signals over serial audio interfaces (IIS/EIAJ)
and over digital audio interfaces (IEC958).
module, the memory map and register definitions, and a programming example.
of record files.
debug support. The topics discussed are real-time trace support, background
Module”:The Chip Select Module provides user-programmable control of the
This chapter describes the BootROM operation, the boot modes, and creation
This chapter provides the system configuration and protocol of the I
This chapter provides signal descriptions, operation, memory map,
This chapter provides the DMA signal descriptions, memory map,
Interface”:This chapter describes the operation of the bus interface to
MCF5253 Reference Manual, Rev. 1
Modules”:
(AIM)”:This chapter discusses the audio interface structure,
(SIM)”:This chapter describes the operation, memory map, and
(ADC)”:
Interface”:
This chapter describes the configuration and operation of
This chapter explains the ADC operation, memory
Module”:
This chapter details the MCF5253 hardware
This chapter describes the operation of
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