MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 550

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
24.9.11 Ping Control
USB 2.0 defines an addition to the protocol for high-speed devices called Ping. Ping is required for all USB
2.0 High-speed bulk and control endpoints. Ping is not allowed for a split-transaction stream. This
extension to the protocol eliminates the bad side-effects of Naking OUT endpoints. The Status field has a
Ping State bit, which the host controller uses to determine the next actual PID it will use in the next
transaction to the endpoint (see
queue heads that meet all of the following criteria:
Table 24-66
PING protocol. Refer to Chapter 8 in the USB Specification, Revision 2.0 for detailed description on the
Ping protocol.
The Ping State bit is described in
on the initialization of the ping protocol (that is, start in Do OUT when we don't know whether there is
space on the device or not). The host controller manages the Ping State bit. The system software sets the
initial value in the queue head when it initializes a queue head. The host controller preserves the Ping State
bit across all queue advancements. This means that when a new qTD is written into the queue head overlay
area, the previous value of the Ping State bit is preserved.
24-88
•
•
•
The queue head is not an interrupt
The EPS field equals High-Speed
The PIDCode field equals OUT
illustrates the state transition table for the host controller's responsibility for maintaining the
1
2
3
Transaction Error (XactErr) is any time the host misses the handshake.
No transition change required for the Ping State bit. The Stall handshake
results in the endpoint being halted (for example, Active cleared and Halt
set). Software intervention is required to restart queue.
A Nyet response to an OUT means that the device has accepted the data,
but cannot receive any more at this time. Host must advance the transfer
state and additionally, transition the Ping State bit to Do Ping.
Current
Do OUT
Do OUT
Do OUT
Do OUT
Do OUT
Do Ping
Do Ping
Do Ping
Do Ping
Table
Table 24-66. Ping Control State Transition
Table
MCF5253 Reference Manual, Rev. 1
24-53). The Ping State bit is only managed by the host controller for
PING
PING
PING
PING
Host
OUT
OUT
OUT
OUT
OUT
24-53. The defined ping protocol allows the host to be imprecise
Event
XactErr
XactErr
Device
Nyet
Stall
Stall
Nak
Nak
Ack
Ack
1
1
Do Ping
Do OUT
Do OUT
Do Ping
Do Ping
Do Ping
Do Ping
Next
N/C
N/C
2
2
3
Freescale Semiconductor