MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 85

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

9. If field is “000”, divide by 8
10. Fvcxo min. 200 MHz max. is 400 MHz
11. This bit controls power-down.
12. Faudio is the audio clock. It is LRCK3/AUDIOCLK/GPIO43 when address pin A20/A24 is connected with a pull-up to Vdd, it
4.2.1
The input to the PLL is either CRIN, or CRIN divided by two. Selection is done by CRSEL. The PLL
divides this input frequency by a programmable division factor (PLLDIV). In the PLL phase/frequency
detector, this divided clock is compared with the VCXO output clock divided by (VCXODIV). As a result,
Fvcxo = Fin × (2 × VCXODIV) / (PLLDIV).
In a second step, this VCXO clock is divided by (VCXOOUT * CPUDIV) to create the CPU clock
PSTCLK.
The multiplexers that switch between PLL clock and CRIN is glitch-free, so no system reset is needed
when switching between bypass and PLL modes.
4.2.2
PLL lock time is typically around 10 ms.
4.2.3
Due to implementation of the block, some limits apply to the PLL block. These limitations are shown in
Table
Freescale Semiconductor
is CRIN or CRIN/2 when address pin A20/A24 is connected with a pull-down to GND.
4-5.
Fin/PLLDIV
PLL Operation
PLL Lock-In Time
PLL Electrical Limits
Name
Fvcxo
Fcpu
The PLL lock counter is designed for worst case audio input frequency (Fin)
of 33.8688 MHz. This will result in the required 0.5 ms for the PLL to lock.
Other Fin frequencies can be used, however, the resulting lock time will be
slightly longer.
It is important that before reprogramming the PLL division factors, users
must switch to PLL bypass mode. After reprogramming, users may
immediately switch back to PLL enabled mode. Switching back is delayed
internally until the PLL is locked.
Frequency MHz
Minimum
200
0
2
MCF5253 Reference Manual, Rev. 1
Table 4-5. PLL Electrical Limits
Frequency MHz
Maximum
400
140
8
NOTE
NOTE
PLL limitations
Maximum operating frequency of device
PLL limitations
Reason
Phase-Locked Loop and Clock Dividers
4-5