MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 339

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

The block encoder works on the incoming PDOR3 stream. First, CRC insertion is done in the CRC
Calculate and Insert block (1), next the stream is scrambled in the Scramble block (2), and finally it is
byte-swapped in the Swap Bytes Block (3). All three operations can be configured by writing to the
blockControl register. CRC insertion and scrambling are done as described in CD Yellow Book.
The CRC insertion (1) and the Scrambling (2) are done on a block-by-block basis. A block is normally
2352 bytes long. A block starts after the so-called sync Pattern, “00FFFFFF-FFFFFFFF-FFFFFF00”. To
detect the start of a new block, two mechanisms are build into the encoder.
17.7.8.2
17.8
It is possible to use the DMA to transfer data to/from the FIFO’s in the audio interface module. However,
only PDIR2 and PDOR3 registers support DMA transfer, as the others need more than 1 long-word to
transfer data to/from the FIFO and cannot be used with DMA operation.
Operation is as follows:
Freescale Semiconductor
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First long-word of a new block is assumed after finding the sync pattern
“00FFFFFF-FFFFFFFF-FFFFFF00”
First long-word of a new block is assumed exactly 2352 bytes after the first longword of the
previous block. This second detection mechanism builds in immunity for corrupted syncs. Even if
the sync is corrupted, the block encoder will correctly find the start of the a new block.
newBlock interrupt—Active when transmission of a new block is started. No direct
synchronization with data written to the transmit
noSync interrupt—Set when the sync pattern was not recognized for the current newBlock
interrupt.
ilSync interrupt—Set when the previous block did not have the correct length. (Length different
from 2352 bytes).
If PDIR2 is full and DMAConfig(1) is set to ‘0’, DMA1REQ is activated.
DMA Channel Interaction
CD-ROM Encoder Interrupts
Processor
Data
Sync
Recognition
Sync Settings
CRC
calculate
and
insert
4
MCF5253 Reference Manual, Rev. 1
Figure 17-22. Block Encoder
1
newBlockInt
ilSyncInt
noSyncInt
Scramble
On/Off select
FIFO
2
.
Swap select
Swap
Bytes
3
To
audio
data
bus
Audio Interface Module (AIM)
17-41