MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 141

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Bus Operation
Figure 8-12. Line Write Burst with One Wait State
Figure 8-13. Line Write Burst-Inhibited
8.6
Misaligned Operands
All MCF5253 data formats can be located in memory on any byte boundary. A byte operand is properly
aligned at any address; a word operand is misaligned at an odd address; and a longword is misaligned at
an address that is not evenly divisible by four. Unlike opcodes, because operands can reside at any byte
boundary, they are allowed to be misaligned. Although the MCF5253 does not enforce any alignment
restrictions for data operands (including program counter (PC) relative data addressing), some
performance degradation occurs when additional bus cycles are required for longword or word operands
that are misaligned. For maximum performance, data items should be aligned on their natural boundaries.
All instruction words and extension words (opcodes) must reside on word boundaries. An address error
exception will occur with any attempt to prefetch an instruction word at an odd address.
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
8-13