MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 483

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

24.6.3.4
In host mode, this register is used by the controller to index the periodic frame list. The register updates
every 125 microseconds (once each microframe). Bits [N–3] are used to select a particular entry in the
Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on
the size of the frame list as set by the system software in the Frame List Size field in the USBCMD register.
Freescale Semiconductor
Field
SRE
URE
PCE
UEE
AAE
SEE
FRE
UE
7
6
5
4
3
2
1
0
SOF Received Enable. This is a non-EHCI bit that is present on the USB OTG module. When this bit is a one, and the
SOF Received bit in the USBSTS register is a one, the controller will issue an interrupt. The interrupt is acknowledged
by the software clearing the SOF Received bit.
1 Enable.
0 Disable.
USB Reset Enable. This is a non-EHCI bit that is present on the USB OTG module only. When this bit is a one, and the
USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is
acknowledged by the software clearing the USB Reset Received bit. Used only in device mode.
1 Enable.
0 Disable.
Interrupt on Async Advance Enable. When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS
register is a one, the controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by
the software clearing the Interrupt on Async Advance bit. Only used in host mode.
1 Enable.
0 Disable.
System Error Enable. When this bit is a one, and the System Error bit in the USBSTS register is a one, the controller
will issue an interrupt. The interrupt is acknowledged by the software clearing the System Error bit.
1 Enable.
0 Disable.
Frame List Rollover Enable. When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the
controller will issue an interrupt. The interrupt is acknowledged by the software clearing the Frame List Rollover bit.
Used only in host mode.
1 Enable.
0 Disable.
Port Change Detect Enable. When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one,
the controller will issue an interrupt. The interrupt is acknowledged by the software clearing the Port Change Detect bit.
1 Enable.
0 Disable.
USB Error Interrupt Enable. When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the
controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by the software clearing
the USBERRINT bit in the USBSTS register.
1 Enable.
0 Disable.
USB Interrupt Enable. When this bit is a one, and the USBINT bit in the USBSTS register is a one, the controller will
issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by the software clearing the USBINT bit.
1 Enable.
0 Disable.
Table 24-17. USB Interrupt Enable (USBINTR) Register Field Descriptions (continued)
Frame Index Register (FRINDEX)
MCF5253 Reference Manual, Rev. 1
Description
Universal Serial Bus Interface
24-21