MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 487

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

24.6.3.9
This register is not defined in the EHCI specification. For the module in device mode, this register contains
the address of the top of the endpoint list in system memory. Bits [10–0] of this register cannot be modified
by the system software and always return zeros when read. The memory structure referenced by this
physical memory pointer is assumed to be 64-bytes. The queue head is actually a 48-byte structure, but
must be aligned on 64-byte boundary. However, the ENDPOINTLISTADDR[EPBASE] has a granularity
of 2 Kbytes, so in practice the queue head should be 2-Kbyte aligned.
This register is shared between the host and device mode functions. In device mode, it is the
ENDPOINTLISTADDR register; in host mode, it is the ASYNCLISTADDR register. See
Section 24.6.3.8, “Current Asynchronous List Address Register (ASYNCLISTADDR),”
information.
Freescale Semiconductor
ASYBASE
Address MBAR2 0x758 (Host Mode)
Field
31–5
Reset
Reset
4–0
Table 24-22. Current Asynchronous List Address (ASYNCLISTADDR) Register Field Descriptions
W
W
R
R
31
15
Link Pointer Low (LPL). These bits correspond to memory address signal [31:5]. This field may reference only a
Queue Head (QH). Used only by the host controller.
Reserved.
0
0
Endpoint List Address Register (ENDPOINTLISTADDR), Non-EHCI
Figure 24-20. Current Asynchronous List Address (ASYNCLISTADDR) Register
30
14
0
0
29
13
0
0
28
12
0
0
ASYBASE(con’t)
27
11
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
25
0
0
9
ASYBASE
Description
24
0
0
8
23
0
0
7
22
0
0
6
21
0
0
5
20
0
0
4
Universal Serial Bus Interface
19
0
0
3
Access: User read/write
18
for more
0
0
2
17
0
0
1
24-25
16
0
0
0