MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 92

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Instruction Cache
the value contained in the 2-bit CLNF field of the CACR and the miss address.
relationship between the CLNF bits, the miss address, and the size of the external fetch.
Depending on the runtime characteristics of the application and the memory response speed, overall
performance may be increased by programming the CLNF bits to values {00, 01}.
For all cases of a line-sized fetch, the critical longword defined by bits [3:2] of the miss address is accessed
first followed by the remaining three longwords that are accessed by incrementing the longword address
in a modulo-16 fashion is shown in the following example code:
Once an external fetch has been initiated and the data loaded into the line-fill buffer, the instruction cache
maintains a special “most-recently-used” indicator that tracks the contents of the fill buffer versus its
corresponding cache location. At the time of the miss, the hardware indicator is set, marking the fill buffer
as “most recently used.” If a subsequent access occurs to the cache location defined by bits [8:4] of the fill
buffer address, the data in the cache memory array is now most recently used, so the hardware indicator is
cleared. In all cases, the indicator defines whether the contents of the line fill buffer or the memory data
array are most recently used. At the time of the next cache miss, the contents of the line-fill buffer are
written into the memory array if the entire line is present, and the fill buffer data is still most recently used
compared to the memory array.
The fill buffer can also be used as temporary storage for line-sized bursts of non-cacheable references
under control of CACR[10]. With this bit set, a noncacheable instruction fetch is processed as defined by
Table
the data is never loaded into the memory array.
Table 5-2
5-4
5-2. For this condition, the fill buffer is loaded and subsequent references can hit in the buffer, but
if miss address[3:2] = 00
fetch sequence = {$0, $4, $8, $C}
if miss address[3:2] = 01
fetch sequence = {$4, $8, $C, $0}
if miss address[3:2] = 10
fetch sequence = {$8, $C, $0, $4}
if miss address[3:2] = 11
fetch sequence = {$C, $0, $4, $8}
shows the relationship between CACR bits 31 and 10 and the type of instruction fetch.
CLNF[1:0]
00
01
1X
Table 5-1. Initial Fetch Offset versus CLNF Bits
Line
Line
Line
00
MCF5253 Reference Manual, Rev. 1
Longword Address Bits
Line
Line
Line
01
Longword
Line
Line
10
Longword
Longword
Table 5-1
Line
11
Freescale Semiconductor
shows the