MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 259

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

programming bit 2 of UMR1. UMR1 should also be programmed before enabling the transmitter and
loading the corresponding data bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it
is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and loads the character into the
receiver holding register FIFO, provided the received A/D bit is a one (address tag). The character is
discarded if the received A/D bit is a zero (data tag). If the receiver is enabled, all received characters are
transferred to the CPU using the receiver holding register stack during read operations.
In either case, the data bits are loaded into the data portion of the stack while the A/D bit is loaded into the
status portion of the stack normally used for a parity error (USR bit 5). Framing error, overrun error, and
break detection operate normally. The A/D bit takes the place of the parity bit; therefore, parity is neither
calculated nor checked. Messages in this mode can still contain error detection and correction information.
One way to provide error detection, if 8-bit characters are not required, is to use software to calculate parity
and append it to the 5-, 6-, or 7-bit character.
15.3.5
This section describes the operation of the bus during read, write, and interrupt- acknowledge cycles to the
UART module. All UART module registers must be accessed as bytes.
15.3.5.1
The CPU accesses the UART module with 1 to 2 wait states because the core system clock is divided by
2 for the UART module. The UART module responds to reads with byte data on D[7:0]. Reserved registers
return logic zero during reads.
15.3.5.2
The CPU with zero wait states accesses the UART module. The UART module accepts write data on
D[7:0]. Write cycles to read-only registers and reserved registers complete in a normal manner without
exception processing; however, the data is ignored.
15.3.5.3
The UART module can arbitrate for interrupt servicing and supply the interrupt vector when it has
successfully won arbitration. The vector number must be provided if interrupt servicing is necessary; thus,
the interrupt vector register (UIVR) must be initialized. The interrupt vector number generated by the IVR
is used if the autovector is not enabled in the SIM Interrupt Control Register (ICR). If the UIVR is not
initialized and the ICR is not programmed for autovector, a spurious interrupt exception is taken if
interrupts are generated. This works in conjunction with the MCF5253 interrupt controller, which allows
a programmable Interrupt Priority Level (IPL) for the interrupt.
15.4
This section contains a detailed description of each register and its specific function as well as flowcharts
of basic UART module programming.
Freescale Semiconductor
UART Memory Map and Register Definitions
Bus Operation
Read Cycles
Write Cycles
Interrupt Acknowledge Cycles
MCF5253 Reference Manual, Rev. 1
UART Modules
15-13