MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 42

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

MCF5253 Introduction
three registers provide a write path to the audio bus and can be selected by transmitters as the audio source.
Through these registers, the CPU has access to the audio samples for processing.
Audio can be routed from a receiver to a transmitter without the data being processed by the core so the
audio bus can be used as a digital audio data switch. The audio bus can also be used for audio format
conversion.
1.5.16
The MCF5253 is capable of processing CD-ROM sectors in hardware. Processing is compliant with
CD-ROM and CD-ROM XA standards.
The CD-ROM decoder performs the following functions in hardware:
The CD-ROM encoder performs the following functions in hardware:
1.5.17
Three full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats
can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte
receive buffers and two-byte transmit buffers minimize CPU service calls. The Triple UART module also
provides several error-detection and maskable-interrupt capabilities. Modem support includes
request-to-send (RTS) and clear-to-send (CTS) lines for UART0/1. The third UART lacks request-to-send
and clear-to-send lines.
The system clock provides the clocking function from a programmable prescaler. Users can select full
duplex, auto-echo loopback, local loopback, and remote loopback modes. The programmable triple
UARTs can interrupt the CPU on numerous events.
1.5.18
The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to
16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to
1-10
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Sector sync recognition
Descrambling of sectors
Verification of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors
Third-layer error correction (ECC) is not performed in hardware. It is not essential to do
Third-layer error correction but should it be determined for a particular application then a s/w
Third-layer error correction is available.
Sector sync recognition
Scrambling of sectors
Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors.
Third-layer error encoding needs to be done in software. This can use approximately 5-10 MHz of
performance for single-speed.
CD-ROM Encoder/Decoder
Three UART Modules
Queued Serial Peripheral Interface
MCF5253 Reference Manual, Rev. 1
QSPI
Freescale Semiconductor