MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 615

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Register (USBSTS),”
information.
24.12.5 Embedded Design
This is an Embedded USB Host Controller as defined by the EHCI specification and thus does not
implement the PCI configuration registers.
24.12.5.1 Frame Adjust Register
Given that the optional PCI configuration registers are not included in this implementation, there is no
corresponding bit level timing adjustments like those provided by the Frame Adjust register in the PCI
configuration registers. Starts of microframes are timed precisely to 125 µsec using the transceiver clock
as a reference clock. That is, 60 MHz transceiver clock for 8-bit physical interfaces and full-speed serial
interfaces or 30 MHz transceiver clock for 16-bit physical interfaces.
24.12.6 Miscellaneous Variations from EHCI
24.12.6.1 Programmable Physical Interface Behavior
The modules support multiple physical interfaces which can operate in different modes when the module
is configured with the software programmable Physical Interface Modes. The control bits for selecting the
PHY operating mode have been added to the PORTSC n register providing a capability that is not defined
by the EHCI specification.
24.12.6.2 Discovery
24.12.6.2.1 Port Reset
The port connect methods specified by EHCI require setting the port reset bit in the register for a duration
of 10 msec. Due to the complexity required to support the attachment of devices that are not high speed
there are counter already present in the design that can count the 10 msec reset pulse to alleviate the
requirement of the software to measure this duration. Therefore, the basic connection is then summarized
as the following:
Freescale Semiconductor
•
•
•
•
[Port Change Interrupt] Port connect change occurs to notify the host controller driver that a device
has attached.
The software shall write a ‘1’ to the reset the device.
The software shall write a ‘0’ to the reset the device after 10 msec.
— This step, which is necessary in a standard EHCI design, may be omitted with this
[Port Change Interrupt] Port enable change occurs to notify the host controller that the device in
now operational and at this point the port speed has been determined.
implementation. Should the EHCI host controller driver attempt to write a ‘0’ to the reset bit
while a reset is in progress the write will simple be ignored and the reset will continue until
completion.
and
Section 24.6.3.3, “USB Interrupt Enable Register (USBINTR),”
MCF5253 Reference Manual, Rev. 1
Universal Serial Bus Interface
for more
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