MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 611

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

24.12.1.3 Discovery
In a standard EHCI controller design, the EHCI host controller driver detects a Full speed (FS) or Low
speed (LS) device by noting if the port enable bit is set after the port reset operation. The port enable will
only be set in a standard EHCI controller implementation after the port reset operation and when the host
and device negotiate a High-Speed connection (that is, Chirp completes successfully).
The module will always set the port enable after the port reset operation regardless of the result of the host
device chirp result and the resulting port speed will be indicated by the PSPD field in PORTSC n .
Therefore, the standard EHCI host controller driver requires an alteration to handle directly connected Full
and Low speed devices or hubs. The change is a fundamental one in that is summarized in
24.12.1.4 Data Structures
The same data structures used for FS/LS transactions though a HS hub are also used for transactions
through the Root Hub. Here it is demonstrated how the Hub Address and Endpoint Speed fields should be
set for directly attached FS/LS devices and hubs:
Freescale Semiconductor
After port enable bit is set following a connection
and reset sequence, the device/hub is assumed to
be HS.
FS and LS devices are assumed to be
downstream from a HS hub thus, all port-level
control is performed through the Hub Class to the
nearest Hub.
FS and LS devices are assumed to be
downstream from a HS hub with HubAddr=X.
[where HubAddr > 0 and HubAddr is the address
of the Hub where the bus transitions from HS to
FS/LS (that is, Split target hub)]
1. QH (for direct attach FS/LS) – Async. (Bulk/Control Endpoints) Periodic (Interrupt)
•
•
•
2. siTD (for direct attach FS) – Periodic (ISO Endpoint)
Hub Address = 0
Transactions to direct attached device/hub.
— QH.EPS = Port Speed
Transactions to a device downstream from direct attached FS hub.
— QH.EPS = Downstream Device Speed
Maximum Packet Size must be less than or equal 64 or undefined behavior may result.
Table 24-93. Functional Differences Between EHCI and EHCI with Embedded TT
Standard EHCI
When QH.EPS = 01 (LS) and PORTSC n [PSPD] = 00 (FS), a LS-pre-pid
will be sent before the transmitting LS traffic.
MCF5253 Reference Manual, Rev. 1
After port enable bit is set following a connection and reset sequence, the
device/hub speed is noted from PORTSCn.
FS and LS device can be either downstream from a HS hub or directly
attached. When the FS/LS device is downstream from a HS hub, then
port-level control is done using the Hub Class through the nearest Hub.
When a FS/LS device is directly attached, then port-level control is
accomplished using PORTSCn.
FS and LS device can be either downstream from a HS hub with HubAddr
= X [HubAddr > 0] or directly attached [where HubAddr = 0 and HubAddr
is the address of the Root Hub where the bus transitions from HS to FS/LS
(that is, Split target hub is the root hub)]
NOTE
EHCI with Embedded Transaction Translator
Universal Serial Bus Interface
Table
24-93.
24-149