MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 166

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
9.7.1.1
PARK register field bits [1:0] are programmed to indicate the priority of internal transfers. The possible
masters that can initiate internal transfers are the core and the on-chip DMAs. Since the priority between
DMAs is resolved by their relative priority amongst each other and by programming the BWC bits in their
respective DMA control registers (see
MPARK bits need only arbitrate priority between the core and the DMA module (which contains all four
DMA channels) for internally generated transfers.
There are four arbitration schemes that the MPARK[1:0] bits can be programmed to with respect to
internally generated transfers. The following summarizes these schemes when EARBCTRL=0:
9-22
1. Round Robin Scheme (PARK[1:0]=00)—In this scenario, depending on which master has priority
2. Park on Master Core Priority (PARK[1:0]=01)—Any time arbitration is occurring or the bus is idle,
3. Park on Master DMA Priority (PARK[1:0]=10)—Any time arbitration is occurring or the bus is
4. Park on Current Master Priority (PARK[1:0]=11)—Whatever the current master is, they have
Address MBAR + $0c
Reset
in the current transfer, the other master has priority in the next transfer once the current master has
finished. When the processor is initialized, the core has first priority.
the core has priority. The DMA module can arbitrate a transfer only when the core’s internal bus
request signal is negated.
idle, the DMA has priority. The core can arbitrate a transfer only when the DMA’s internal bus
request signal is negated.
priority. Only when the bus is idle can the other master gain ownership and priority of the bus. For
example, if out of reset the core has priority it will continue to have priority until the bus becomes
idle. Then when the DMA asserts its internal bus request signal, it will then have priority.
W
R
So for example, if the core is the bus master and is finishing a bus transfer and DMA channels
0 and 1 (both set to BWC=010) are asserting an internal bus request signal, then the DMA
channel 0 would gain ownership of the bus after the core; but after channel 0 finishes its
transfer, the core would have ownership of the bus if its request was asserted.
PARK[1]
Internal Arbitration Operation
The Internal DMA has higher priority than the ColdFire Core if the internal
DMA has its bandwidth BWC[2:0] bits set to 000 (maximum bandwidth).
0
7
PARK[0]
0
6
Figure 9-14. Default Bus Master Register (MPARK)
IARBCTRL
MCF5253 Reference Manual, Rev. 1
Section 14.4, “DMA Memory Map and Register
0
5
EARBCTRL
NOTE
0
4
SHOWDATA
0
3
0
2
Freescale Semiconductor
Access: User read/write
Definitions”), the
0
1
BCR24BIT
0
0