MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 133

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

The bus signals transition on the rising edge of BCLK. The strobe signals CSx, OE make their transitions
on the falling edge of BCLK. Read data is latched on the rising edge of BCLK.
The bus supports byte, word, and longword operand transfers and uses a 16-bit data port. With the
MCF5253, the port size of all memory must be programmed to 16 bits, the internal transfer termination
must be enabled, and the number of wait states must be set for the external slave being accessed by
programming the Chip-Select Control Registers (CSCRs) and the DRAM Controller Control Registers
(DCRs). For more information on programming these registers, refer to
Operation,”
Figure 8-3
the sequential transfers that would occur for each memory if a longword was transferred to it. A 16-bit
memory should be connected to[31:16] of the MCF5253 data bus. For a longword transfer, the most
significant word D[31:16] will be transferred on lane D[31:16], followed by the least significant word
being transferred.
8.5.1
When a bus cycle is initiated, the processor compares the address of that bus cycle with the base address
and mask configurations programmed for various memory-mapped peripherals. These include SRAM0,
SRAM1, System Bus Controller 1 and 2, chip selects, and the DRAM. If no match is found, the cycle will
Freescale Semiconductor
3. Data bus (D[31:16])
4. Strobe (CSx, OE)
shows the byte lanes that external chip-select memory and DRAM should be connected to and
Bus Cycle Execution
and
Section 7.3.1, “DRAM Controller Registers.”
Figure 8-2. Connections for External Memory Port Sizes
Processor External
Data Bus
16-Bit Port Memory
8-Bit Port Memory
Driver with
Indeterminate Values
MCF5253 Reference Manual, Rev. 1
D[31:24]
Byte 0
Byte 2
Byte 0
Byte 1
Byte 2
Byte 3
D[23:16]
Byte 1
Byte 3
Section 10.3, “Chip Select
Bus Operation
8-5