MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 122

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Synchronous DRAM Controller Module
7.6.1
To interface this component to the MCF5253 DRAM controller, use the connection table that corresponds
to a 16-bit port size with 8 columns
functional.
7.6.2
At power-up, the DCR has the following configuration if synchronous operation and SDRAM address
multiplexing is desired.
This configuration results in a value of 0x8012 for DCR, as shown in
7-18
MCF5253 Pins
SDRAM Pins
Setting
RTIM
NAM
COC
10–9
Bits
8–0
(hex)
SO
RC
Field
15
14
13
12
11
IS
Setting
0x12
00
SO
1
x
0
0
0
15
1
Table 7-13
SDRAM Interface Configuration
DCR Initialization
Indicating synchronous operation
Don’t care (reserved)
Indicating SDRAM controller multiplexes address lines internally
BCLKE is used as clock enable instead of command bit because user is not multiplexing address lines
externally and requires external command feed.
At power-up, allowing power self-refresh state is not appropriate because registers are being set up.
Because t
Specification indicates auto-refresh period for 4096 rows to be 64 mS or refresh every 15.625 µs for each row,
or 312 bus clocks at 40MHz. Because DCR[RC] is incremented by 1 and multiplied by 16, RC = (312 bus
clocks/16) -1 = 18.56 = 0x12
14
–
A16
A0
8
NAM COC
13
0
shows the proper hardware hook-up.
A15
RC
A1
value is 70 nS, indicating a 3-clock refresh-to-
12
0
A14
A2
Table 7-13. SDRAM Hardware Connections
Figure 7-13. Initialization Values for DCR
IS
11
0
A13
A3
Table 7-14. DCR Initialization Values
(Figure
MCF5253 Reference Manual, Rev. 1
10
A12
0
A4
RTIM
0
7-14). Two pins select one of four banks when the part is
A11
0
A5
9
A10
A6
0
8
Description
A9
A7
0
7
A17
A8
0
6
ACTV
A18
A9
1
timing.
Table
0
5
A10 = CMD
A19
RC
7-14.
1
4
0
3
Freescale Semiconductor
A20/A24
A11
0
2
2
BA0
A21
1
1
BA1
A22
0
0