MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 167

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

9.7.1.2
The following tables show the encoding for the PARK[1:0] bit of the MPARK register along with the
priority schemes for each encoding.
Table 9-22
master has current ownership of the bus (i.e. has highest priority), the next arbitration cycle will switch
priority to master that had lowest priority on that prior current cycle.
Freescale Semiconductor
Current Highest
Current Highest
Priority Master
Priority Master
shows the round robin configuration of internal module arbitration. Depending on which
Core
DMA
Core
DMA
PARK Register Bit Configuration
Table 9-23. Park on Master DMA Module Priority (PARK[1:0] = 10)
Table 9-24. Park on Current Master Priority (PARK[1:0] = 11)
Current Lowest
Priority Master
Table 9-22. Park on Master Core Priority (PARK[1:0] = 01)
Table 9-20. Default Bus Master Selected with PARK[1:0]
Current Lowest
Park[1:0]
Priority Master
DMA
Core
00
01
10
11
DMA
Core
Table 9-21. Round Robin (PARK[1:0] = 00)
Priority
Priority
Highest
Highest
Lowest
Lowest
MCF5253 Reference Manual, Rev. 1
Round Robin between DMA and ColdFire Core
Park on master ColdFire Core
Park on master DMA Module
Park on current master
Next Arbitration Cycle Highest
Next Arbitration Cycle Highest
Priority Master
Default Bus Master Number
Priority Master
DMA
Core
Bus Master Name
Bus Master Name
DMA
Core
ColdFire Core
ColdFire Core
Internal DMA
Internal DMA
Next Arbitration Cycle Lowest
Next Arbitration Cycle Lowest
Priority Master
System Integration Module (SIM)
Priority Master
DMA
Core
DMA
Core
9-23