MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 627

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

25.5.3
This register represents a 16-bit free running counter that can be read and written to by the CPU. The timer
starts from 0x0000 after reset, counts linearly to 0xFFFF, and wraps around.
The timer is clocked by the FlexCAN bit-clock (which defines the baud rate on the CAN bus). During a
message transmission/reception, it increments by one for each bit that is received or transmitted. When
there is no message on the bus, it counts using the previously programmed baud rate. During freeze mode,
the timer is not incremented.
The timer value is captured at the beginning of the identifier (ID) field of any frame on the CAN bus. This
captured value is written into the TIMESTAMP entry in a message buffer after a successful reception or
transmission of a message.
Writing to the timer is an indirect operation. The data is first written to an auxiliary register, then an internal
request/acknowledge procedure across clock domains is executed. All this is transparent to the user, except
for the fact that the data will take some time to be actually written to the register. If desired, software can
poll the register to discover when the data was actually written.
25.5.4
These registers are used as acceptance masks for received frame IDs. Three masks are defined: a global
mask (RXGMASK n ) used for Rx buffers 0–13, 16–31 and two separate masks for buffers 14
(RX14MASK n ) and 15 (RX15MASK n ). The meaning of each mask bit is the following:
MI n bit = 0: The corresponding incoming ID bit is “don’t care”.
MI n bit = 1: The corresponding ID bit is checked against the incoming ID bit, to see if a match exists.
Note that these masks are used both for standard and extended ID formats. The value of the mask registers
should not be changed while in normal operation (only while in freeze mode), as locked frames that
matched a message buffer (MB) through a mask may be transferred into the MB (upon release) but may
no longer match.
Freescale Semiconductor
TIMER
31–16
Offset MBAR2 0x1008 (TIMER0)
Field
Reset 0
15–0
W
R 0
MBAR2 0x2008 (TIMER1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved, should be cleared.
Free running timer. Captured at the beginning of the identifier (ID) field of any frame on the CAN bus. This captured
value is written into the TIMESTAMP entry in a message buffer after a successful reception or transmission of a
message.
FlexCAN Free Running Timer Register (TIMERn)
Rx Mask Registers (RXGMASKn, RX14MASKn, RX15MASKn)
0
0
0
0
0
0
Table 25-4. FlexCAN Timer (TIMERn) Register Field Descriptions
0
0
0
0
0
0
Figure 25-6. FlexCAN Timer (TIMERn) Register
0
0
0
0
0
0
MCF5253 Reference Manual, Rev. 1
0
0
0
0
0
0
0
0
0
0
Description
0
0
0
0
0
0
0
0
9
0
TIMER
0
8
0
7
Access: User read/write
0
6
0
5
0
4
FlexCAN Module
0
3
0
2
0
25-11
1
0
0