MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 101

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
(SRAM1 Only)
(SRAM1 Only)
C/I, SC, SD,
PRI1, PRI2
Bit Name
(SRAM1)
(SRAM)
UC, UD
31–14
13–12
11–10
13–9
SPV
WP
7–6
5–1
BA
V
9
8
0
The Base Address field defines the modulo-64K base address of the SRAM module. The SRAM memory
occupies a 64 Kbyte space defined by the contents of the Base Address field. By programming this field, the
SRAM may be located on any 64 Kbyte boundary within the processor’s four gigabyte address space.
Reserved, should be cleared.
The PRI1 priority bit determines if DMA or CPU has priority in upper 32k bank of memory. PRI2 determines if
DMA or CPU has priority in lower 32k bank of memory. If bit is set, DMA has priority. If bit is reset, CPU has
priority. Priority is determined by the following table:
Allow DMA access
0 DMA access to memory is disabled.
1 DMA access to memory is enabled.
The Write Protect field allows only read accesses to the SRAM. When this bit is set, any attempted write
access will generate an access error exception to the ColdFire processor core.
0 Allows read and write accesses to the SRAM module
1 Allows only read accesses to the SRAM module
Reserved, should be cleared.
Address Space Masks (ASn)
These five bit fields allow certain types of accesses to be “masked,” or inhibited from accessing the SRAM
module. The address space mask bits are:
C/ICPU space/interrupt acknowledge cycle mask
SCSupervisor code address space mask
SDSupervisor data address space mask
UCUser code address space mask
UDUser data address space mask
For each address space bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. If a reference using this address space is made, it is
inhibited from accessing the SRAM module, and is processed like any other non-SRAM reference.
These bits are useful for power management as detailed in
The valid bit. A hardware reset clears this bit. When set, this bit enables the SRAM module; otherwise, the
module is disabled.
0 Contents of RAMBAR are not valid
1 Contents of RAMBAR are valid
Table 6-1. SRAM(1) Base Address Register (RAMBARn) Field Descriptions
MCF5253 Reference Manual, Rev. 1
PRI[1:2]
2’b00
2’b01
2’b10
2’b11
DMA Accesses
DMA Accesses
CPU Accesses
CPU Accesses
Upper Bank
Description
Priority
Section 6.3.4, “Power
DMA Accesses
DMA Accesses
CPU Accesses
CPU Accesses
Lower Bank
Priority
Management.”
Static RAM (SRAM)
6-3