MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 51

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

2.2
Many pins have an optional GPIO function.
2.3
The signals discussed in this section provide the external bus interface to the MCF5253.
2.3.1
The address bus provides the address of the byte or most significant byte of the word or longword being
transferred.The address lines also serve as the DRAM address pins, providing multiplexed row and column
address signals.
Freescale Semiconductor
High Impedance
Debug Data
Processor Status
Processor clock
Test Clock
Test Reset/
Development Serial
Clock
Test Mode Select/Break
Point
Test Data Input/
Development Serial
Input
Test Data
Output/Development
Serial Output
•
•
•
Signal Name
General purpose input is always active, regardless of state of pin.
General purpose output or primary output is determined by the appropriate setting of the Pin
Multiplex Control Registers, GPIO-FUNCTION, GPIO1-FUNCTION and PIN-CONFIG.
At Power-on reset all pins are set to their primary function.
GPIO
MCF5253 Bus Signals
Address Bus
PSTCLK/GPIO51
HI_Z
DDATA0/CTS1/SDATA0_SDIO1/GPIO1
DDATA1/RTS1/SDATA2_BS2/GPIO2
DDATA2/CTS0/GPIO3
DDATA3/RTS0/GPIO4
PST0/GPIO50
PST1/GPIO49
PST2/INTMON2/GPIO48
PST3/INTMON1/GPIO47
TCK
TRST/DSCLK
TMS/BKPT
TDI/DSI
TDO/DSO
Table 2-1. MCF5253 Signal Index (continued)
Mnemonic
MCF5253 Reference Manual, Rev. 1
Assertion tri-states output signal pins
Display of captured processor data
and break-point statuses
Indication of internal processor status.
Processor clock output
Clock signal for IEEE 1149.1A JTAG
Multiplexed signal that is
asynchronous reset for JTAG
controller. Also, clock input for debug
module.
Multiplexed signal that is test mode
select in JTAG mode and a hardware
break-point in debug mode
Multiplexed serial input for the JTAG or
background debug module.
Multiplexed serial output for the JTAG
or background debug module
Function
Output
Input/
In/Out
In/Out
Out
Out
Signal Description
In
In
In
In
In
Reset
State
Hi_Z
Hi_Z
–
–
–
–
–
–
2-5