MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 40

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

MCF5253 Introduction
1.5.4
The instruction cache improves system performance by providing cached instructions to the execution unit
in a single clock cycle. The MCF5253 processor uses an 8K-byte, direct-mapped instruction cache to
achieve 125 MIPS at 140 MHz. The cache is accessed by physical addresses, where each 16-byte line
consists of an address tag and a valid bit. The instruction cache also includes a bursting interface for 16-bit
and 8-bit port sizes to quickly fill cache lines.
1.5.5
The 128-Kbyte on-chip SRAM is split over two banks, SRAM0 (64K) and SRAM1 (64K). It provides
single clock-cycle access for the ColdFire core. This SRAM can store processor stack and critical code or
data segments to maximize performance. Memory in the second bank (SRAM1) can be accessed under
DMA.
1.5.6
The MCF5253 DRAM controller provides a glueless interface for one bank of DRAM, and can address up
to 32MB. The controller supports a 16-bit data bus. The controller operates in page mode, non-page mode,
and burst-page mode and supports SDRAMs.
1.5.7
The MCF5253 provides a glueless interface to 16-bit port size SRAM, ROM, and peripheral devices with
independent programmable control of the assertion and negation of chip-select and write-enable signals.
The MCF5253 also supports bursting ROMs.
1.5.8
The bus interface controller transfers data between the ColdFire core or DMA and memory, peripherals,
or other devices on the external bus. The external bus interface provides 23 address lines, a 16-bit data bus,
Output Enable, and Read/Write signals. This interface implements an extended synchronous protocol that
supports bursting operations.
1.5.9
The USB module in the MCF5253 is used for communication to a PC or communication to slave devices,
e.g. to download data from a hard disc player to a flash player, to a photo printer and so on. The USB
supports full Host mode functionality. The USB supports the OTG supplement to the USB 2.0
specification. It operates as high speed, full speed and low speed host, and as high speed and full speed
device. Host negotiation protocol (HNP) and session request protocol (SRP) are implemented with
software support.
A USB 2.0 high-speed compatible PHY is integrated on-chip.
1-8
Instruction Cache
Internal 128-Kbyte SRAM
DRAM Controller
System Interface
External Bus Interface
USB 2.0 High-Speed On-The-Go
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor