MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 490

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
24-28
TXSCHHEALTH
TXFIFOTHRES
Address MBAR2 0x764
TXSCHOH
Reset
Reset
31–22
21–16
15–13
Field
12–8
7–0
W
W
R
R
Table 24-25. Transmit FIFO Tuning Controls (TXFILLTUNING) Register Field Descriptions
31
15
0
0
Reserved.
FIFO Burst Threshold. These bits control the number of data bursts that are posted to the TX latency FIFO in
host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as
possible to maximize USB performance. A higher value can be used in systems with unpredictable latency
and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency
FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream
Disable bit in USBMODE register is set. When the SDIS bit is set, the host controller behaves as if
TXFIFOTHRES is set to the maximum value.
Reserved.
Scheduler Health Counter. These bits increment when the host controller fails to fill the TX latency FIFO to the
level programmed by TXFIFOTHRES before running out of time to send the packet before the next
Start-Of-Frame.
This health counter measures the number of times this occurs to provide feedback to selecting a proper
TXSCHOH. Writing to this register clears the counter and this counter stops counting after reaching the
maximum of 31.
Scheduler Overhead. These bits add an additional fixed offset to the schedule time estimator described above
as T
captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is
too high for this register is not desired as it can needlessly reduce USB utilization.
The time unit represented in this register is 1.267μs when a device is connected in High-Speed Mode.
The time unit represented in this register is 6.333μs when a device is connected in Low/Full-speed Mode.
For most applications, TXSCHOH can be set to 4 or less. A good value to begin with is: TXFIFOTHRES *
(BURSTSIZE * 4 bytes-per-word) / (40 * TimeUnit), always rounded to the next higher integer. TimeUnit is
either 1.267 or 6.333 as noted earlier in this description. For example, if TXFIFOTHRES is 5 and BURSTSIZE
is 8, then set TXSCHOH to 5*(8*4)/(40*1.267) = 4 for a high-speed link. If this value of TXSCHOH results in a
TXSCHHEALTH count of 0 per second, try lowering the value by 1 if optimizing performance is desired. If
TXSCHHEALTH exceeds 10 per second, try raising the value by 1.
If streaming mode is disabled via the USBMODE register, treat TXFIFOTHRES as the maximum value for
purposes of the TXSCHOH calculation.
30
14
0
0
Figure 24-23. Transmit FIFO Tuning Controls (TXFILLTUNING) Register
ff
. As an approximation, the value chosen for this register should limit the number of back-off events
29
13
0
0
28
12
0
0
27
11
TXSCHHEALTH
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
25
0
0
9
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
0
5
TXSCHOH
20
0
0
4
TXFIFOTHRES
19
0
0
3
Freescale Semiconductor
Access: User read/write
18
0
0
2
17
0
0
1
16
0
0
0