MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 138

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Bus Operation
8.5.5
When burst read enable or burst write enable is asserted into the relevant chip select register, the MCF5253
will initiate burst cycles any time a transfer size is larger than the port size the MCF5253 is transferring to.
A line transfer to a 16-bit port would constitute a burst cycle of eight words of data.
The MCF5253 bus can support 3-2-2-2 burst cycles to maximize cache performance and optimize DMA
transfers. Users can add wait states if desired by delaying termination of the cycle.
Through the chip select control registers, users can enable bursting on reads, bursting on writes or bursting
on both reads and writes if desired.
8.5.5.1
A line is defined as a 16-byte value, aligned in memory on 16-byte boundaries. Although the line itself is
aligned on 16-byte boundaries, the line access does not necessarily begin on the aligned address.Therefore,
the bus interface supports line transfers on multiple address boundaries. The allowable patterns during a
line access are shown in
8.5.5.2
Figure 8-8
8-10
D[31:16]
A[31:0]
BCLK
CSx
OE
shows a line access read with zero wait states.
RW
Burst Cycles
TA
Line Transfers
Line Read Bus Cycles
Table
S0
8-8.
Table 8-8. Allowable Line Access Patterns
Addr[3:2]
S1
Figure 8-7. Back-to-Back Bus Cycle
00
01
10
11
MCF5253 Reference Manual, Rev. 1
S2
S3
Read
S4
S5
Longword Accesses
S0
0 - 4 - 8 - C
4 - 8 - C - 0
8 - C - 0 - 4
C - 0 - 4 - 8
S1
S2
Write
S3
S4
Freescale Semiconductor
S5