MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 201

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

To support this bus set-up, a number of signals are available.
The extra bus signals, and their configuration are detailed in the following section.
13.1.1
Buffer enables BUFENB1 and BUFENB2 allow a seamless interface to external bus buffers. The buffers
are placed on the address and the data bus.
As shown in
before the falling edge of the Chip Select signal, and continue to be active for a time CSPOST after the
rising edge of the chip select signal. The pre-drive time CSPRE is realized by delaying the falling edge of
the select signal. If pre-drive time CSPRE is programmed non-zero, and internal ColdFire cycle
termination is used, chip select length will be CSPRE shorter than the programmed length. Times CSPRE,
CSPOST are the same for both BUFENB1 AND BUFENB2. Times CSPRE, CSPOST are independently
programmable for every Chip Select.
Buffer enable configuration is programmable using the IDE_CONFIG1 register.
Freescale Semiconductor
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BUFENB1—active-low external buffer enable. This enable is always active when the CS0/CS4
pin is active, and should enable a buffer going to the external boot Flash / ROM and any additional
memories or controllers.
When CS0 is being used internally as the Chip Select for the boot ROM, the CS0/CS4 pin operates
with the CS4 settings, BUFENB1 settings then apply to CS4.
BUFENB2—active-low external buffer enable. This enable is always inactive when the CS0/CS4
pin is active, and should enable a buffer for the IDE / SmartMedia Interface.
IDE_DIOR, IDE_DIOW—active-low IDE bus read and write strobe can also be used to implement
a SmartMedia interface.
IDE_IORDY—active-high “ready” indication from IDE device to MCF5253.
CS0, CS1,
DIOR, DIOW, SRE, SWE
Buffer Enables BUFENB1, BUFENB2, and Associated Logic
Figure
Either of the buffer enables can be programmed to be active on CS1 or CS2
13-2, the buffer enables BUFENB1 and BUFENB2 will go active at time CSPRE
CSx_core
BUFENBx
bufenx_b
Figure 13-2. Buffer Enables (BUFENB1 and BUFENB2)
MCF5253 Reference Manual, Rev. 1
CSPRE
cspre
NOTE
CSPOST
cspost
IDE and Flash Media Interface
13-3