MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 534

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
24.9.6
Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries
The USB Specification Revision 2.0 requires that the frame boundaries (SOF frame number changes) of
the high-speed bus and the full- and low-speed bus(es) below USB 2.0 hubs be strictly aligned.
Super-imposed on this requirement is that USB 2.0 hubs manage full- and low-speed transactions via a
micro-frame pipeline (see start- (SS) and complete- (CS) splits illustrated in
Figure
24-45). A simple,
direct projection of the frame boundary model into the host controller interface schedule architecture
creates tension (complexity for both hardware and software) between the frame boundaries and the
scheduling mechanisms required to service the full- and low-speed transaction translator periodic
pipelines.
Frame
Boundary
Micro-Frame
7
0
1
2
3
4
5
6
7
0
1
Numbers
HS Bus
SS
CS
CS
CS
SS
CS
CS
CS
CS
CS
FS/LS Bus
Figure 24-45. Frame Boundary Relationship between HS Bus and FS/LS Bus
The simple projection, as
Figure 24-45
illustrates, introduces frame-boundary wrap conditions for
scheduling on both the beginning and end of a frame. In order to reduce the complexity for hardware and
software, the host controller is required to implement a one micro-frame phase shift for its view of frame
boundaries. The phase shift eliminates the beginning of frame and frame-wrap scheduling boundary
conditions.
The implementation of this phase shift requires that the host controller use one register value for accessing
the periodic frame list and another value for the frame number value included in the SOF token. These two
values are separate, but tightly coupled. The periodic frame list is accessed via the Frame List Index
Register (FRINDEX). Bits FRINDEX[2:0], represent the micro-frame number. The SOF value is coupled
to the value of FRINDEX[13:3]. Both FRINDEX[13:3] and the SOF value are incremented based on
FRINDEX[2:0]. It is required that the SOF value be delayed from the FRINDEX value by one
micro-frame. The one micro-frame delay yields a host controller periodic schedule and bus frame
boundary relationship as illustrated in
Figure
24-46. This adjustment allows the software to trivially
schedule the periodic start and complete-split transactions for full-and low-speed periodic endpoints, using
the natural alignment of the periodic schedule interface.
Figure 24-46
illustrates how periodic schedule data structures relate to schedule frame boundaries and bus
frame boundaries. To aid the presentation, two terms are defined. The host controller's view of the
1-millisecond boundaries is called H-Frames. The high-speed bus's view of the 1-millisecond boundaries
is called B-Frames.
MCF5253 Reference Manual, Rev. 1
24-72
Freescale Semiconductor