MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 27

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

About This Book
The MCF5253 is designed as a system controller/decoder for compressed audio music players addressing
both portable and automotive solutions supporting CD, HDD and USB based systems. The 32-bit
ColdFire
and code density for the combination of control code and signal processing required for compressed audio
decode, file management, and system control.
Audience
The MCF5253 Reference Manual is intended to provide a design engineer with the necessary data to
successfully integrate the MCF5253 into a wide variety of applications. It is assumed that the reader
understands operating systems, microprocessor system design, basic principles of software and hardware,
and basic details of the ColdFire architecture.
Organization
The MCF5253 Reference Manual is organized into 26 chapters that cover the operation and programming
of the MCF5253 device. Summaries of the chapters follow.
Chapter 1, “MCF5253
Chapter 2, “Signal
Chapter 3, “ColdFire
Chapter 4, “Phase-Locked Loop and Clock
Chapter 5, “Instruction
Chapter 6, “Static RAM
Chapter 7, “Synchronous DRAM Controller
Chapter 8, “Bus
Freescale Semiconductor
®
core with an enhanced multiply and accumulate (eMAC) unit provides optimum performance
Operation”:This chapter describes bus functionality, the bus control signals, and the bus
Description”:
Core”:
Introduction”:
Cache”:
processor and general descriptions of the MCF5253 features and modules.
into functional groups.
The chapter describes the CFV2 memory map and register definitions as
implemented on the MCF5253. It also includes a full description of exception
handling, data formats, an instruction set summary, and a table of instruction
timings.
the operation and programming of the clock generation module as well as the
recommended circuit settings. It also describes the audio clock generation and the
system power states.
and register definitions for the MCF5253 instruction cache.
definitions, initialization, and SRAM power management.
map, register definitions, signal and command descriptions, and an interface
example for the SDRAM controller.
cycles provided for data-transfer operations. Bus operation is defined for transfers
initiated by the MCF5253 as a bus master and for transfers initiated by an alternate
(SRAM)”:
This chapter provides an overview of the MCF5253 microprocessor core.
This chapter describes the physical organization, operation, memory map,
This chapter describes the MCF5253 input and output signals, organized
This chapter describes the SRAM operation, memory map, register
MCF5253 Reference Manual, Rev. 1
This chapter provides an overview of the MCF5253 ColdFire®
Dividers”:
Module”:
This chapter provides detailed information about
This chapter discusses the operation, memory
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