MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 624

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

FlexCAN Module
25.5.2
CANCTRL n is defined for specific FlexCAN control features related to the CAN bus, such as bit-rate,
programmable sampling point within an Rx bit, loop back mode, listen-only mode, bus off recovery
behavior, and interrupt enabling. It also determines the division factor for the clock prescaler. Most of the
fields in this register should only be changed while the module is disabled or in freeze mode. Exceptions
are the BOFFMSK, ERRMSK, and BOFFREC bits, which can be accessed at any time.
25-8
SOFTRST
FRZACK
LPMACK
MAXMB
22–21
SUPV
Field
19–5
5–0
25
24
23
20
Table 25-2. FlexCAN Configuration Register (CANMCRn) Field Descriptions (continued)
Soft reset. When set, the FlexCAN resets its internal state machines (sequencer, error counters, error flags, and
timer) and the host interface registers (CANMCRn [except the MDIS bit], TIMER, ERRCNT, ERRSTAT, IMASK, and
IFLAG).
The configuration registers that control the interface with the CAN bus are not changed (CANCTRLn, RXGMASKn,
RX14MASKn, RX15MASKn). Message buffers are also not changed. This allows SOFTRST to be used as a debug
feature while the system is running.
Since soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may
take some time to fully propagate its effect. The SOFTRST bit remains set while reset is pending and is
automatically cleared when reset completes. The user should poll this bit to know when the soft reset has
completed.
0 Soft reset cycle completed
1 Soft reset cycle initiated
Freeze acknowledge. Indicates that the FlexCAN module has entered freeze mode. The user should poll this bit
after freeze mode has been requested, to know when the module has actually entered freeze mode. When freeze
mode is exited, this bit is cleared once the FlexCAN prescaler is enabled. This is a read-only bit.
0 The FlexCAN has exited freeze mode and the prescaler is enabled.
1 The FlexCAN has entered freeze mode, and the prescaler is disabled.
Supervisor/user data space. Places the FlexCAN registers in either supervisor or user data space.
0 Registers with access controlled by the SUPV bit are accessible in either user or supervisor privilege mode.
1 Registers with access controlled by the SUPV bit are restricted to supervisor mode.
Reserved, should be cleared.
Low power mode acknowledge. Indicates that FlexCAN is disabled. Disabled mode cannot be entered until all
current transmission or reception processes have finished, so the CPU can poll the LPMACK bit to know when the
FlexCAN has actually entered low power mode. See
information. This bit is read-only.
0 FlexCAN not disabled.
1 FlexCAN is in disabled mode.
Reserved, should be cleared.
Maximum number of message buffers. Defines the maximum number of message buffers that will take part in the
matching and arbitration process. The reset value (0x1F) is equivalent to 32 message buffer (MB) configuration.
This field should be changed only while the module is in freeze mode.
Note:
FlexCAN Control Register (CANCTRLn)
Maximum MBs in Use = MAXMB + 1
MCF5253 Reference Manual, Rev. 1
Description
Section 25.3.2.3, “Module Disabled Mode”
Freescale Semiconductor
for more