MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 346

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

I
18.2
The MCF5253 provides dual I
compatible with the I
The I
between devices. This two-wire bus minimizes the interconnection between devices.
The I
between many devices. The flexible I
and system development.
The interface operates up to 100 kbps with maximum bus loading and timing. Operation can be extended
to operate at the high speed I
adhere to the I
the number of devices that can be attached to a high speed I
18-2
2
C Modules
2
2
C is a two-wire, bidirectional serial bus that provides a simple and efficient method of data exchange
C bus is suitable for applications requiring occasional communications over a short distance
I
2
C Overview
2
C bus timing specification load capacitance will have to be carefully controlled, to this end
CTRL_REG
ADDR_DECODE
2
C Bus Standard.
CONTROL
SYNC
INPUT
CLOCK
ADDR
2
C specification (400 kbps) but this requires careful thought and design. To
2
C interface capability. The I
FREQ_REG
Figure 18-1. I
REGISTERS AND COLDFIRE INTERFACE
2
MCF5253 Reference Manual, Rev. 1
C allows additional devices to be connected to the bus for expansion
START, STOP, AND
SCL
ARBITRATION
CONTROL
2
ADDR_REG
C Module Block Diagram
SDA
2
2
C bus interface will be limited. Also the value
C interface described in this chapter is fully
STATUS_REG
IRQ
DATA SHIFT
REGISTER
ADDRESS
COMPARE
IN/OUT
DATA_MUX
DATA_REG
DATA
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