MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 114

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Synchronous DRAM Controller Module
7.4.2
The tables in the previous section can be used to configure the interface in the following example. To
interface one 1M × 16-bit × 4 bank SDRAM component (8 columns) to the MCF5253, the connections
would be as shown in
the AP / CMD.
7.4.3
The SDRAM can efficiently provide data when an SDRAM page is opened. As soon as SDCAS is issued,
the SDRAM accepts a new address and asserts SDCAS every clock for as long as accesses are in that page.
In burst page mode, there are multiple read or write operations for every
if the requested transfer size exceeds the port size of the associated SDRAM. The first cycle of the transfer
generates the
commands. As soon as the transfer completes, the
access.
Figure 7-6
delay (t
data out), this value is 2 BCLK cycles. Notice that
command is executed one cycle after the last data transfer.
7-10
SDRAM Pins
MCF5253 Pins
MCF5253 Pins
Row
Column
Output during CAS
Output during RAS
SDRAM Pins
RCD
shows a burst read operation. In this example, DACR[CASL] = 01, for an SRAS-to-SCAS
) of 1 BCLKO cycle. Because t
Interfacing Example
Burst Page Mode
ACTV
In synchronous operation, burst mode and address incrementing during
burst cycles are controlled by the MCF5253 DRAM controller. Thus,
instead of the SDRAM enabling its internal burst incrementing capability,
the MCF5253 controls this function. This means that the burst function that
is enabled in the mode register of SDRAMs must be disabled when
interfacing to the MCF5253.
A16 A15 A14 A13 A12 A11 A10 A9 A17 A18
A0
Table 7-10. SDRAM Interface (16-Bit Port, 9-Column Address Lines)
and
A16
A16
A1
A0
A1
16
Table
1
READ
A2
A15
A15
A2
A1
15
2
7-11. Pin A20/A24 is programmed to A20 mode and A19 is programmed as
or
Table 7-11. SDRAM Hardware Connections
A3
WRITE
A14
A14
A3
A2
14
3
A4
MCF5253 Reference Manual, Rev. 1
A13
A14
A13
A3
13
commands; additional cycles generate only
4
A5
RCD
A12
A12
A5
A4
12
5
is one more than the read CAS latency (SCAS assertion to
A6
NOTE
A11
A11
PALL
A5
11
A6
NOP
6
A7
s are executed until the last data is read. A
A10
A10
command is generated to prepare for the next
A8
A6
A7
10
7
A9
A9
A8
A9
A7
9
8
A21
A20
A21
A10=CMD
A8
21
20
A19
A17
A16
A17
A9
17
ACTV
–
A20/A24
A18
A11
A17
A18
18
–
command in the SDRAM
A11
A19
A18
A19
A12
READ
19
Freescale Semiconductor
–
BA0/A12
A21
A22
A22
A10
AP
or
22
–
WRITE
A23
A13
A23
A23
23
–
BA1/A13
PALL
A22
A24
A24
A24
A14
24
–