MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 542

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
to the Asynchronous Schedule Enable bit in the USBCMD register. The software then can poll the
Asynchronous Schedule Status bit to determine when the asynchronous schedule has made the desired
transition. The software must not modify the Asynchronous Schedule Enable bit unless the value of the
Asynchronous Schedule Enable bit equals that of the Asynchronous Schedule Status bit.
The asynchronous schedule is used to manage all Control and Bulk transfers. Control and Bulk transfers
are managed using queue head data structures. The asynchronous schedule is based at the
ASYNCLISTADDR register. The default value of the ASYNCLISTADDR register after reset is undefined
and the schedule is disabled when the Asynchronous Schedule Enable bit is cleared.
The software may only write this register with defined results when the schedule is disabled, for example,
Asynchronous Schedule Enable bit in the USBCMD and the Asynchronous Schedule Status bit in the
USBSTS register are cleared. The system software enables execution from the asynchronous schedule by
writing a valid memory address (of a queue head) into this register. Then the software enables the
asynchronous schedule by setting the Asynchronous Schedule Enable bit is set. The asynchronous
schedule is actually enabled when the Asynchronous Schedule Status bit is set.
When the host controller begins servicing the asynchronous schedule, it begins by using the value of the
ASYNCLISTADDR register. It reads the first referenced data structure and begins executing transactions
and traversing the linked list as appropriate. When the host controller completes processing the
asynchronous schedule, it retains the value of the last accessed queue head's horizontal pointer in the
ASYNCLISTADDR register. Next time the asynchronous schedule is accessed, this is the first data
structure that is serviced. This provides round-robin fairness for processing the asynchronous schedule.
A host controller completes processing the asynchronous schedule when one of the following events
occur:
The queue heads in the asynchronous list are linked into a simple circular list as shown in
Queue head data structures are the only valid data structures that may be linked into the asynchronous
schedule. An isochronous transfer descriptor (iTD or siTD) in the asynchronous schedule yields undefined
results.
The maximum packet size field in a queue head is sized to accommodate the use of this data structure for
all non-isochronous transfer types. The USB Specification, Revision 2.0 specifies the maximum packet
sizes for all transfer types and transfer speeds. The system software should always parameterize the queue
head data structures according to the core specification requirements.
24.9.9.1
This is a software requirement section. There are two independent events for adding queue heads to the
asynchronous schedule. The first is the initial activation of the asynchronous list. The second is inserting
a new queue head into an activated asynchronous list.
24-80
•
•
•
The end of a micro-frame occurs.
The host controller detects an empty list condition.
The schedule has been disabled via the Asynchronous Schedule Enable bit in the USBCMD
register.
Adding Queue Heads to Asynchronous Schedule
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
Figure
24-44.