MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 74

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
3.5.11
If a CF2 processor encounters any type of fault during the exception processing of another fault, the
processor immediately halts execution with the catastrophic “fault-on-fault” condition. A reset is required
to force the processor to exit this halted state.
3.5.12
Asserting the reset input signal to the processor causes a reset exception. The reset exception has the
highest priority of any exception; it provides for system initialization and recovery from catastrophic
failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot
be recovered.
The reset exception places the processor in the supervisor mode by setting the S bit and disables tracing
by clearing the T bit in the SR. This exception also clears the M bit and sets the processor’s interrupt
priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero ($00000000). The
control registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected
directly to the processor are disabled.
After reset is negated, the core performs two longword read bus cycles. The first longword at address 0 is
loaded into the stack pointer and the second longword at address 4 is loaded into the program counter. After
the initial instruction is fetched from memory, program execution begins at the address in the PC. If an
access error or address error occurs before the first instruction is executed, the processor enters the
fault-on-fault halted state.
3.6
This section describes CF2 processor instruction execution times in terms of processor core clock cycles.
The number of operand references for each instruction is enclosed in parentheses following the number of
clock cycles. Each timing entry is presented as C(r/w) where:
This section includes the assumptions concerning the timing values and the execution time details.
3.6.1
For the timing data presented in this section, the following assumptions apply:
3-12
•
•
1. The operand execution pipeline (OEP) is loaded with the opword and all required extension words
C—number of processor clock cycles, including all applicable operand fetches and writes, and all
internal core cycles required to complete the instruction execution.
r/w—number of operand reads (r) and writes (w) required by the instruction. An operation
performing a read-modify-write function is denoted as (1/1).
at the beginning of each instruction execution. This implies that the OEP does not wait for the
instruction fetch pipeline (IFP) to supply opwords and/or extension words.
Instruction Execution Timing
Fault-on-Fault Halt
Reset Exception
Timing Assumptions
Other implementation-specific supervisor registers are also affected.
Refer to each of the modules in this manual for details on these registers.
MCF5253 Reference Manual, Rev. 1
NOTE
Freescale Semiconductor