MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 594

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
24.11.3 Managing Endpoints
The USB 2.0 specification defines an endpoint, also called a device endpoint or an address endpoint as a
uniquely addressable portion of a USB device that can source or sink data in a communications channel
between the host and the device. The endpoint address is specified by the combination of the endpoint
number and the endpoint direction.
The channel between the host and an endpoint at a specific device represents a data pipe. Endpoint 0 for a
device is always a control type data channel used for device discovery and enumeration. Other types of
endpoints support by USB include bulk, interrupt, and isochronous. Each endpoint type has specific
behavior related to packet response and error handling. More detail on endpoint operation can be found in
the USB 2.0 specification.
The USB_DR supports up to six(6) endpoint specified numbers. The DCD can enable, disable and
configure each endpoint.
Each endpoint direction is essentially independent and can be configured with differing behavior in each
direction. For example, the DCD can configure endpoint 1-IN to be a bulk endpoint and endpoint 1-OUT
to be an isochronous endpoint. This helps to conserve the total number of endpoints required for device
operation. The only exception is that control endpoints must use both directions on a single endpoint
number to function as a control endpoint. Endpoint 0 is, for example, is always a control endpoint and uses
the pair of directions.
Each endpoint direction requires a queue head allocated in memory. If the maximum of 6 endpoint
numbers, one for each endpoint direction are being used by the device controller, then 12 queue heads are
required. The operation of an endpoint and use of queue heads are described later in this document.
24.11.3.1 Endpoint Initialization
After a hardware reset, all endpoints except endpoint zero are uninitialized and disabled. The DCD must
configure and enable each endpoint by writing to configuration bit in the ENDPTCTRLn register. Each
32-bit ENDPTCTRLn is split into an upper and lower half. The lower half of ENDPTCTRLn is used to
configure the receive or OUT endpoint and the upper half is likewise used to configure the corresponding
transmit or IN endpoint. Control endpoints must be configured the same in both the upper and lower half
of the ENDPTCTRLn register otherwise the behavior is undefined.
configuration word for endpoint initialization.
24-132
Data Toggle Reset
Data Toggle Inhibit
Before resume signaling can be used, the host must enable it by using the
Set Feature command defined in USB 2.0 Specification, Chapter 9, Device
Framework.
Table 24-81. Device Controller Endpoint Initialization
Field
MCF5253 Reference Manual, Rev. 1
NOTE
1
0
Table 24-81
Value
shows how to construct a
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