MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 617

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Chapter 25
FlexCAN Module
This chapter discusses the modes of operation, signals, memory map, register descriptions, and the
functional and initialization sequence of the FlexCAN controller of the MCF5253.
25.1
Following are the main features of the FlexCAN module:
25.2
A block diagram describing the various submodules of the FlexCAN module is shown in
Each submodule is described in detail in subsequent sections. The message buffer architecture is shown in
Figure
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
•
•
25-2.
Full implementation of the CAN protocol specification version 2.0B
— Standard data and remote frames (up to 109 bits long)
— Extended data and remote frames (up to 127 bits long)
— 0–8 bytes data length
— Programmable bit rate up to 1 Mbps
— Content-related addressing
Up to 32 flexible message buffers of zero to eight bytes data length, each configurable as Rx or Tx,
all supporting standard and extended messages
Listen-only mode capability
Three programmable mask registers: global (for MBs 0–13 and 16–31), special for MB14, and
special for MB15
Programmable transmission priority scheme: lowest ID or lowest buffer number
Time stamp based on 16-bit, free-running timer
Global network time, synchronized by a specific message
Programmable I/O modes
Maskable interrupts
Independent of the transmission medium (an external transceiver is assumed)
Open network architecture
Multimaster bus
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Features
Block Diagram
MCF5253 Reference Manual, Rev. 1
Figure
25-1.
25-1