MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 183

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
Address MBAR + 0x84 (CSMR0)
Reset
Reset
15–9, 7
W
W
31–16
R BAM
R
Field
BAM
WP
8
MBAR + 0x90 (CSMR1)
MBAR + 0x9C (CSMR2)
MBAR + 0xA8 (CSMR3)
MBAR + 0xB4 (CSMR4)
31
31
15
–
–
BAM
The Base Address Mask field defines the chip select block size through the use of address mask bits. Any
set bit masks the corresponding base address register (CSAR) bit (the base address bit becomes a don’t
care in the decode).
0 Corresponding address bit is used in chip select decode
1 Corresponding address bit is a don’t care in chip select decode
The block size for all CS are equal to 2
the respective CSMR + 16).
For example, if CSAR0 were set at $0000 and CSMR0 were set at $0008, then chip select CS0 would
address two discontinuous memory blocks of 64Kbytes each: the first block would be from $00000000 to
$0000FFFF and the second block would be from $00080000 to $0008FFFF. Stated another way, if any of
the upper 16-bits in the CSMR0 were set, then the corresponding address bit is a don’t care in the chip
select decode.
Another example might be if CS0 were to access 32MBs of address space starting at location $0 and CS1
has to begin at the next byte after CS0 for an address space of 16MB. Then:
CSAR0 = $0000, (upper 16 bits of) CSMR0 = $01FF, and
CSAR1 = $0200, (upper 16 bits of) CSMR1 = $00FF.
Reserved
The Write Protect bit can restrict write accesses to the address range in a CSAR. An attempt to write to the
range of addresses specified in a CSAR that has this bit set results in the appropriate chip select not being
selected. No exception occurs.
0 Both read and write accesses are allowed.
1 Only read access is allowed.
30
30
14
–
–
Table 10-4. Chip Select Mask Register (CSMRx) Field Descriptions
BAM
29
29
13
–
–
BAM
28
28
12
–
–
Figure 10-2. Chip Select Mask Register (CSMRx)
BAM
27
27
11
–
–
MCF5253 Reference Manual, Rev. 1
BAM
26
26
10
–
–
Address Space Mask Bits
BAM
25
25
–
–
9
n
, where n = (number of bits set in the base address mask field of
BAM
WP
24
24
–
–
8
Description
BAM
23
23
–
–
7
BAM
AM
22
22
–
–
6
BAM
21
C/I
21
–
–
5
BAM
SC
20
20
–
–
4
BAM
SD
19
19
–
–
3
Access: User read/write
BAM
UC
18
18
–
–
2
Chip Select Module
BAM
UD
17
17
–
–
1
BAM
16
16
10-7
V
–
0
0