MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 292

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Queued Serial Peripheral Interface (QSPI) Module
16.4.2
16.4.3
16-10
Address MBAR + 0x404
Address MBAR + 0x408
Field
14–8
QCD
SPE
DTL
WREN
7–0
WRTO
15
HALT
Field
Reset
Reset
15
14
13
W
W
R
R
QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the command RAM.
Automatically cleared by the QSPI when a transfer completes.The user can also clear this bit to abort transfer unless
QIR[ABRTL] is set. The recommended method for aborting transfers is to set QWR[HALT].
QSPILCK Delay. When the DSCK bit in the command RAM, is set this field determines the length of the delay from
assertion of the chip selects to valid QSPI_CLK transition.
Delay after transfer. When the DT bit in the command RAM sets this field, it determines the length of delay after the serial
transfer.
SPE
Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands once it has completed execution
of the current command.
Wraparound enable. Enables wraparound mode.
0 Execution stops after executing the command pointed to by QWR[ENDQP].
1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed to by
Wraparound location. Determines where the QSPI wraps to in wraparound mode.
0 Wrap to RAM entry zero.
1 Wrap to RAM entry pointed to by QWR[NEWQP].
HALT
15
0
15
0
QWR[NEWQP] and continue execution.
QSPI Delay Register (QDLYR)
QSPI Wrap Register (QWR)
WREN
14
0
14
0
Table 16-4. QSPI Delay Register (QDLYR) Field Descriptions
13
Table 16-5. QSPI Wrap Register (QWR) Field Descriptions
0
WRTO
13
0
12
0
Figure 16-5. QSPI Delay Register (QDLYR
Figure 16-6. QSPI Wrap Register (QWR)
CSIV
QCD
12
0
11
0
MCF5253 Reference Manual, Rev. 1
11
0
10
1
10
ENDQP
0
0
9
Description
Description
9
0
0
8
0
8
0
7
0
7
6
0
6
CPTQP
0
0
5
0
5
4
0
0
DTL
4
Freescale Semiconductor
Access: User read/write
Access: User read/write
0
3
0
3
NEWQP
1
0
2
2
0
1
0
1
0
0
0
0