MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 269

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

15.4.6
The receiver buffer (URB) contains three receiver-holding registers and a serial shift register. The RxD pin
is connected to the serial shift register while the holding registers act as a FIFO. The CPU reads from the
top of the stack while the receiver shifts and updates from the bottom of the stack when the shift register
has been filled (see
15.4.7
The transmitter buffer (UTB) consists of two registers: the transmitter-holding register and the transmitter
shift register (see
bit in the channel's USR is set. A write to the transmitter buffer clears the TxRDY bit, inhibiting additional
characters until the shift register is ready to accept more data. When the shift register is empty, it checks
the holding register for a valid character to be sent (TxRDY bit cleared). If a valid character is present, the
shift register loads the character and reasserts the TxRDY bit in the USR. Writes to the transmitter buffer
when the channel's UART Status Register (USR) TxRDY bit is clear and when the transmitter is disabled
have no effect on the transmitter buffer.
Freescale Semiconductor
Address MBAR + $1CC (URB0)
Address MBAR + $1CC (UTB0)
RB7–RB0
Reset
Reset
Field
7–0
W
W
R
R
MBAR + $20C (URB1)
MBAR2 + $C0C (URB2)
MBAR + $20C (UTB1)
MBAR2 + $C0C (UTB2)
Receiver Buffer Registers (UBRn)
Transmitter Buffer Registers (UTBn)
RB7
TB7
1
7
0
7
These bits contain the character in the receiver buffer.
Figure
Figure
Table 15-12. Receiver Buffer (URBn) Register Field Descriptions
15-4). The holding register accepts characters from the bus master if the TxRDY
RB6
TB6
1
15-4).
6
6
0
Figure 15-14. Transmitter Buffer (UTBn) Register
Figure 15-13. Receiver Buffer (URBn) Register
MCF5253 Reference Manual, Rev. 1
RB5
TB5
1
5
0
5
RB4
TB4
1
4
0
4
Description
RB3
TB3
1
3
0
3
RB2
TB2
0
1
2
2
Access: User write only
Access: User read only
TB1
RB1
0
1
1
1
UART Modules
TB0
RB0
0
0
1
0
15-23