MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 532

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
register, the host controller also generates an interrupt on the resume event. The software acknowledges
the resume event interrupt by clearing the Port Change Detect status bit in the USBSTS register.
[1] Hardware interrupt issued if Port Change Interrupt Enable bit in the USBINTR register is set.
[2] PME# asserted if enabled (Note: PME Status must always be set).
[3] PME# not asserted.
24.9.5
The host controller executes transactions for devices using a simple, shared-memory schedule. The
schedule is comprised of a few data structures, organized into two distinct lists. The data structures are
designed to provide the maximum flexibility required by USB and minimize memory traffic and
hardware/software complexity.
The system software maintains two schedules for the host controller: a periodic schedule and an
asynchronous schedule. The root of the periodic schedule is the PERIODICLISTBASE register. See
Section 24.6.3.6, “Periodic Frame List Base Address Register (PERIODICLISTBASE),”
information. The PERIODICLISTBASE register is the physical memory base address of the periodic
frame list. The periodic frame list is an array of physical memory pointers. The objects referenced from
the frame list must be valid schedule data structures as defined in
24-70
Port disabled, resume K-State received
Port suspended, Resume K-State received Resume reflected downstream on signaled port. Force Port
Port is enabled, disabled or suspended, and
the port's WKDSCNNT_E bit is set. A
disconnect is detected.
Port is enabled, disabled or suspended, and
the port's WKDSCNNT_E bit is cleared. A
disconnect is detected.
Port is not connected and the port's
WKCNNT_E bit is a one. A connect is
detected.
Port is not connected and the port's
WKCNNT_E bit is a zero. A connect is
detected.
Port is connected and the port's WKOC_E
bit is a one. An over-current condition
occurs.
Port is connected and the port's WKOC_E
bit is a zero. An over-current condition
occurs.
Port Status and Signaling Type
Schedule Traversal Rules
Table 24-63. Behavior During Wake-up Events
MCF5253 Reference Manual, Rev. 1
No Effect
Resume status bit in PORTSC register is set. Port Change
Detect bit in USBSTS register is set.
Depending in the initial port state, the PORTSC Connect and
Enable status bits are cleared, and the Connect Change status
bit is set. Port Change Detect bit in the USBSTS register is set.
Depending on the initial port state, the PORTSC Connect and
Enable status bits are cleared, and the Connect Change status
bit is set. Port Change Detect bit in the USBSTS register is set.
PORTSC Connect Status and Connect Status Change bits are
set. Port Change Detect bit in the USBSTS register is set.
PORTSC Connect Status and Connect Status Change bits are
set. Port Change Detect bit in the USBSTS register is set.
PORTSC Over-current Active, Over-current Change bits are set.
If Port Enable/Disable bit is a one, it is cleared. Port Change
Detect bit in the USBSTS register is set
PORTSC Over-current Active, Over-current Change bits are set.
If Port Enable/Disable bit is a one, it is cleared. Port Change
Detect bit in the USBSTS register is set.
Signaled Port Response
Section 24.8, “Host Data Structures.”
Freescale Semiconductor
for more
[1], [2]
[1], [2]
[1], [3]
[1], [2]
[1], [3]
[1], [2]
[1], [3]
Device State
N/A
D0
not D0
N/A
[2]
[2]
[3]
[2]
[3]
[2]
[3]
In