MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 190

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

General Purpose Timer Modules
11.6.2
The TRR is a 16-bit register that contains the reference value that is compared with its respective,
free-running timer counter (TCN), as part of the output-compare function. TRR is a memory-mapped
read/write register.
TRR is set at reset. The reference value is not matched until TCN equals TRR, and the prescaler indicates
that the TCN should be incremented again. Thus, the reference register is matched after (TRR+1) time
intervals.
11-4
Bit Name
Address MBAR+$144
FRR
RST
CLK
ORI
OM
2–1
Reset
5
4
3
0
W
R
MBAR+$184
Timer Reference Registers (TRR0, TRR1)
1 Toggle output
0 Active-low pulse for one system clock cycle (16.666 ns at 60 MHz)
1 Enable interrupt upon reaching the reference value
0 Disable interrupt for reference reached (does not affect interrupt on capture function)
If ORI is set when the REF event is asserted in the Timer Event Register (TER), an immediate interrupt occurs.
If ORI is cleared while an interrupt is asserted, the interrupt negates.
1 Restart: Timer count is reset immediately after reaching the reference value
0 Free run: Timer count continues to increment after reaching the reference value
11 Invalid
10 SYSCLK divided by 16
The clock source is synchronized with the timer. However, the divider is not reset to 0 when the timer is stopped,
thus successive time-outs may vary slightly in length.
01 SYSCLK
00 Stops counter. After the counter is stopped, the value in the Timer Counter (TCN) register remains constant.
The Reset Timer bit performs a software timer reset identical to that of an external reset. All timer registers take
on their corresponding reset values. While this bit is zero, the other register values can still be written, if
necessary. A transition of this bit from one to zero is what resets the register values. The counter/timer/prescaler
is not clocked unless the timer is enabled.
1 Enable timer
0 Reset timer (software reset)
15
1
Output Mode
Output Reference Interrupt Enable
Free Run/Restart
Input Clock Source for the Timer
Table 11-2. Timer Mode Register (TMRn) Field Descriptions (continued)
14
1
13
1
12
1
Figure 11-3. Timer Reference Register (TRRn)
11
1
MCF5253 Reference Manual, Rev. 1
REFERENCE COMPARE VALUE (REF15–REF0)
10
1
1
9
1
8
Description
1
7
1
6
5
1
Access: Supervisor or User read/write
1
4
1
3
Freescale Semiconductor
1
2
1
1
1
0