MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 406

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Background Debug Mode (BDM) Interface
20.5.6
The CSR defines the debug configuration for the processor and memory subsystem. In addition to defining
the microprocessor configuration, this register also contains status information from the breakpoint logic.
The CSR is cleared during system reset. The CSR can be read and written by the external development
system and written by the supervisor programming model. The CSR is accessible in supervisor mode as
debug control register $0 using the WDEBUG instruction and through the BDM port using the RDMREG
and WDMREG commands.
20-36
EDWU
EDWL
EDUM
EDUU
28, 12
EDLW
27, 11
26, 10
EDLM
EDLL
Field
25, 9
24, 8
23, 7
22, 6
21, 5
20, 4
19, 3
18, 2
17, 1
16, 0
EAR
EPC
EBL
EAL
PCI
EAI
13
DI
If set, the Enable Breakpoint Level bit serves as the global enable for the breakpoint trigger. If cleared, all breakpoints
are disabled.
If set, the Enable Data Breakpoint for the Data Longword bit enables the data breakpoint based on the entire
processor’s local data bus. The assertion of any of the ED bits enables the data breakpoint. If all bits are cleared,
the data breakpoint is disabled.
If set, the Enable Data Breakpoint for the Lower Data Word bit enables the data breakpoint based on the low-order
word of the processor’s local data bus.
If set, the Enable Data Breakpoint for the Upper Data Word bit enables the data breakpoint trigger based on the
high-order word of the processor’s local data bus.
If set, the Enable Data Breakpoint for the Lower Lower Data Byte bit enables the data breakpoint trigger based on
the low-order byte of the low-order word of the processor’s local data bus.
If set, the Enable Data Breakpoint for the Lower Middle Data Byte bit enables the data breakpoint trigger based on
the high-order byte of the low-order word of the processor’s local data bus.
If set, the Enable Data Breakpoint for the Upper Middle Data Byte bit enables the data breakpoint trigger on the
low-order byte of the high-order word of the processor’s local data bus.
If set, the Enable Data Breakpoint for the Upper Upper Data Byte bit enables the data breakpoint trigger on the
high-order byte of the high-order word of the processor’s local data bus.
The Data Breakpoint Invert bit provides a mechanism to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value not equal to the one programmed
into the DBR.
If set, the Enable Address Breakpoint Inverted bit enables the address breakpoint based outside the range defined
by ABLR and ABHR. The assertion of any of the EA bits enables the address breakpoint. If all three bits are cleared,
this breakpoint is disabled.
If set, the Enable Address Breakpoint Range bit enables the address breakpoint based on the inclusive range
defined by ABLR and ABHR.
If set, the Enable Address Breakpoint Low bit enables the address breakpoint based on the address contained in
the ABLR.
If set, the Enable PC Breakpoint bit enables the PC breakpoint.
If set, the PC Breakpoint Invert bit allows execution outside a given region as defined by PBR and PBMR to enable
a trigger. If cleared, the PC breakpoint is defined within the region defined by PBR and PBMR.
Configuration/Status Register (CSR)
Table 20-21. Trigger Definition Register (TDR) Field Descriptions
MCF5253 Reference Manual, Rev. 1
Description
Freescale Semiconductor