MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 504

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
24.6.3.20 Endpoint Complete Register (ENDPTCOMPLETE), Non-EHCI
This register is not defined in the EHCI specification. This register is used by the USB OTG module only
in device mode.
24.6.3.21 Endpoint Control Register 0 (ENDPTCTRL0), Non-EHCI
This register is not defined in the EHCI specification. Every device will implement endpoint 0 as a control
endpoint.
24-42
Address MBAR2 + 0x7BC
31–20
19–16
ERCE
ETCE
Field
15–4
3–0
Reset
Reset
W
W
R
R
Reserved.
Endpoint transmit complete event. Each bit indicates a transmit event (IN/INTERRUPT) occurred and the software
should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set
in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear the
corresponding bit in this register. ETCE[3] (bit 19 of the register) corresponds to endpoint 3.
Reserved.
Endpoint receive complete event. Each bit indicates a received event (OUT/SETUP) occurred and the software should
read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the
Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear the corresponding
bit in this register. ERCE[3] (bit 3 of the register) corresponds to endpoint 3.
31
15
0
0
Table 24-34. Endpoint Complete (ENDPTCOMPLETE) Register Field Descriptions
30
14
0
0
Figure 24-32. Endpoint Complete (ENDPTCOMPLETE) Register
29
13
0
0
28
12
0
0
27
11
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
25
0
0
9
Description
24
0
0
8
23
0
0
7
22
0
0
6
21
0
0
5
20
0
0
4
19
0
0
3
Freescale Semiconductor
Access: User read/write
18
0
0
2
ETCE
ERCE
Clear
Clear
17
0
0
1
16
0
0
0