mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 94

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Resets, Interrupts, and General System Control
5.9.3
This high-page register has three write-once bits and one write-anytime bit. For the write-once bits, only
the first write after reset is honored. All bits in the register can be read at any time. Any subsequent attempt
to write a write-once bit is ignored to avoid accidental changes to these sensitive settings. SOPT must be
written to during the reset initialization program to set the desired controls, even if the desired settings are
the same as the reset settings.
5-12
Field
ILOP
ILAD
POR
COP
LOC
LVD
PIN
7
6
5
4
3
2
1
System Options (SOPT) Register
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source can be blocked by SOPT[COPE] = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. This includes
any illegal instruction [except the ILLEGAL (0x4AFC) opcode] or a privilege violation (execution of a privileged
instruction in user mode). The STOP instruction is considered illegal if stop is disabled by
((SOPT[STOPE] = 0) && (SOPT[WAITE] = 0)). The HALT instruction is considered illegal if the BDM interface is
disabled by XCSR[ENBDM] = 0.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
Illegal Address — Reset was caused by the processor's attempted access of an illegal address in the memory
map, an address error, an RTE format error or the fault-on-fault condition. All the illegal address resets are
enabled when CPUCR[ARD] = 0. When CPUCR[ARD] = 1, then the appropriate processor exception is
generated instead of the reset, or if a fault-on-fault condition is reached, the processor simply halts.
0 Reset not caused by an illegal access.
1 Reset caused by an illegal access.
Loss-of-Clock Reset — Reset was caused by a loss of external clock.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will
occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Table 5-5. SRS Register Field Descriptions
Description
Freescale Semiconductor