mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 140

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

ColdFire Core
7.3.2
Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors
differ from the M68000 family because they include:
All ColdFire processors use an instruction restart exception model. Exception processing includes all
actions from fault condition detection to the initiation of fetch for first handler instruction. Exception
processing is comprised of four major steps:
7-10
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•
•
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1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S
Move from USP
A simplified exception vector table
Reduced relocation capabilities using the vector-base register
A single exception stack frame format
Use of separate system stack pointers for user and supervisor modes.
bit and disabling trace mode by clearing the T bit. The interrupt exception also forces the M bit to
be cleared and the interrupt priority mask to set to current interrupt request level.
Move to USP
CMPI.{B,W}
Instruction
MVS.{B,W}
MVZ.{B,W}
CMP.{B,W}
MOV3Q.L
CMPA.W
STLDSR
SATS.L
MOVEI
BSR.L
TAS.B
Bcc.L
FF1
Exception Processing Overview
Table 7-5. Instruction Enhancements over Revision ISA_A (continued)
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending
with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then
loaded with the offset count from bit 31 where the first set bit appears.
Moves 3-bit immediate data to the destination location.
User Stack Pointer → Destination register
Source register → User Stack Pointer
Sign-extends source operand and moves it to destination register.
Zero-fills source operand and moves it to destination register.
Performs saturation operation for signed arithmetic and updates destination register,
depending on CCR[V] and bit 31 of the register.
Performs indivisible read-modify-write cycle to test and set addressed memory byte.
Branch conditionally, longword
Branch to sub-routine, longword
Compare, byte and word
Compare address, word
Compare immediate, byte and word
Move immediate, byte and word to memory using Ax with displacement
Pushes the contents of the status register onto the stack and then reloads the status register
with the immediate data value.
Description
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